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The purpose of this paper is to present the results of experiments performed to attach silicon dies (chips) to low‐temperature co‐fired ceramic (LTCC) substrates with Ag or AgPd pads using SnAgCu or SnPb solder and the results of the characterization of the solder joints.

LTCC substrates were fabricated by stacking and laminating four green tapes with the top layer screen‐printed with Ag or AgPd paste to form pads. Silicon die sizes of 1 × 1 mm and 2 × 2 mm with electroless nickel immersion gold plated were soldered to 2 × 2 mm pads on the LTCC substrates using SnPb or SnAgCu solder. The solder joints were then characterized using X‐ray, die shear, energy dispersive X‐ray and scanning electron microscopy techniques.

The joints made by AgPd pads with SnAgCu solder provided the best results with the highest shear strength having strong interfaces in the joints. However, the joints of Ag pads with SnPb solder did not provide high‐shear strength.

The findings provide certain guidelines to implement LTCC applications. AgPd pads with SnAgCu solder can be considered for applications where small silicon dies need to be attached to LTCC substrates. However, Ag pads with SnAgCu solder can be considered for lead‐free solder applications.

To study the effects of design and assembly process conditions on lead‐free solder joints for an area array component.

Experiments using SnAgCu solder for assembling plastic ball grid array components on printed circuit boards (PCBs) were carried out to investigate the reliability of the solder joints made under various conditions. The process variables studied include solder pad diameters, solder paste volume and reflow peak temperatures.

The average joint diameter increased with the peak reflow temperature, stencil thickness and pad diameter. The average joint height decreased with the increasing peak reflow temperature and pad diameter. However, increased stencil thickness would lead to increased solder paste volume and therefore increases both joint diameter and height. The assembled boards were subjected to a temperature cycling test (−40 to +125°C) for 5,700 cycles and no failures of the daisy chained resistance loops were found, indicating that the thermal fatigue resistance of the SnAgCu solder joints was good.

The findings provide greater confidence to implement a lead‐free soldering process without compromising reliability. Reliable lead free soldering can be made over a wide process window allowing flexibility in design and manufacturing.

This paper aims to perform experimental test on fatigue characteristics of package on package (POP) stacked chip assembly under thermal cycling load. Some suggestions for design to prolong fatigue life of POP stacked chip assembly are provided.

The POP stacked chip assembly which contains different package structure mode and chip position was manufactured. The fatigue characteristics of POP stacked chip assembly under thermal cycling load were tested. The fatigue load spectrum of POP stacked chip assembly under thermal cycling load was given. The fatigue life of chips can be estimated by using the creep–fatigue life prediction model based on different stress conditions.

The solder joint stress of top package is significantly less than that of bottom solder joints, and the maximum value occurs in the middle part of the solder joints inner ring.

This paper fulfils useful information about the thermal reliability of POP stacked chip assembly with different structure characteristics and materials parameters.

This paper aims to present a machine learning framework for using big data analytics to predict the reliability of solder joints. The purpose of this study is to accurately predict the reliability of solder joints by using big data analytics.

A machine learning framework for using big data analytics is proposed to predict the reliability of solder joints accurately.

A machine learning framework for predicting the life of solder joints accurately has been developed in this study. To validate its accuracy and efficiency, it is applied to predict the long-term reliability of lead-free Sn96.5Ag3.0Cu0.5 (SAC305) for three commonly used surface finishes such OSP, ENIG and IAg. The obtained results show that the predicted failure based on the machine learning method is much more accurate than the Weibull method. In addition, solder ball/bump joint failure modes are identified based on various solder joint failures reported in the literature.

The ability to predict thermal fatigue life accurately is extremely valuable to the industry because it saves time and cost for product development and optimization.

The purpose of this paper is to introduce a novel computational method to evaluate damage accumulation in a solder joint of an electronic package, when exposed to operating temperature environment. A procedure to implement the method is suggested, and a discussion of the method and its possible applications is provided in the paper.

Methodologically, interpolated response surfaces based on specially designed finite element (FE) simulation runs, are employed to compute a damage metric at regular time intervals of an operating temperature profile. The developed method has been evaluated on a finite-element model of a lead-free PBGA256 package, and accumulated creep strain energy density has been chosen as damage metric.

The method has proven to be two orders of magnitude more computationally efficient compared to FE simulation. A general agreement within 3 percent has been found between the results predicted with the new method, and FE simulations when tested on a number of temperature profiles from an avionic application. The solder joint temperature ranges between +25 and +75°C.

The method can be implemented as part of reliability assessment of electronic packages in the design phase.

The method enables increased accuracy in thermal fatigue life prediction of solder joints. Combined with other failure mechanisms, it may contribute to the accuracy of reliability assessment of electronic packages.

This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.

Of the 91 journal papers, 59 were published in 2005‐2007 and topics related to wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging are reviewed.

Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked‐dies wire bonding, wire bonding of low‐k ultra‐fine‐pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead‐free solder joints is being conducted world‐wide. The new challenges, solutions and new developments are discussed in this paper.

Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details.

This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.

The purpose of this paper is to assess the effect of different temperature cycling profiles on the reliability of lead‐free 388 plastic ball grid array (PBGA) packages and to deeply understand crack initiation and propagation.

Temperature cycling of Sn‐3.8Ag‐0.7Cu PBGA packages was carried out at two temperature profiles, the first ranging between −55°C and 100°C (TC1) and the second between 0°C and 100°C (TC2). Crack initiation and propagation was analyzed periodically and totally 7,000 cycles were run for TC1 and 14,500 for TC2. Finite element modeling (FEM), for the analysis of strain and stress, was used to corroborate the experimental results.

The paper finds that TC1 had a characteristic life of 5,415 cycles and TC2 of 14,094 cycles, resulting in an acceleration factor of 2.6 between both profiles. Cracks were first visible for TC1, after 2,500 cycles, and only after 4,000 cycles for TC2. The crack propagation rate was faster for TC1 compared to TC2, and faster at the package side compared to the substrate side. The difference in crack propagation rate between the package side and substrate side was much larger for TC1 compared to TC2. Cracks developed first at the package side, and were also larger compared to the substrate side. The Cu tracks on the substrate side affected the crack propagation sites and behaved as SMD. All cracks propagated through the solder and crack propagation was mainly intergranular. Crack propagation was very random and did not follow the distance to neutral point (DNP) theory. FEM corroborated the experimental results, showing both the same critical location of highest creep strain and the independence of DNP.

Such extensive work on the reliability assessment of Pb‐free 388 PBGA packages has never been performed. This work also corroborates the results from other studies showing the difference in behavior between Pb‐free and Pb‐containing alloys.

This paper attempts to review recent advances in wire bonding using copper wire.

Dozens of journal and conference articles published recently are reviewed.

The problems/challenges such as wire open and short tail defects, poor bondability for stitch/wedge bonds, oxidation of Cu wire, strain‐hardening effects, and stiff wire on weak support structures are briefly analysed. The solutions to the problems and recent findings/developments in wire bonding using copper wire are discussed.

Because of page limitation of the paper, only a brief review is conducted. Further reading is needed for more details.

This paper attempts to provide introduction to recent developments and the trends in wire bonding using copper wire. With the references provided, readers may explore more deeply by reading the original articles.

The purpose of this paper is to review recent advances in wire bonding of low‐k devices.

Dozens of journal and conference articles published in 2005‐2008 are reviewed.

The paper finds that many articles have discussed and analysed problems/challenges such as bond pad metal peeling/lift, non‐sticking on pad, decreased bonding strength and lower wire‐bond assembly yield. The paper discusses the articles' solutions to the problems and recent findings/developments in wire bonding of low‐k devices.

Because of the page limitation, only brief discussions are given in this paper. Further reading is needed for more details.

The paper attempts to provide an introduction to recent developments and the trends in wire bonding of low‐k devices. With the references provided, readers may explore more deeply by reading the original articles.

This paper attempts to review recent advances in wire bonding using insulated wire and new challenges in wire bonding for advanced microelectronics packaging.

Dozens of journal articles, conference articles and patents published or issued in 2004‐2007 are reviewed.

The advantages and problems/challenges related to wire bonding using insulated wire are briefly analysed, and several solutions to the problems and recent findings/developments related to wire bonding using insulated wire are discussed.

Because of page limitation of the paper, only brief review is conducted. Further reading is needed for more details.

This paper attempts to provide introduction to recent developments and the trends in wire bonding using insulated wire. With the references provided, readers may explore more deeply by reading the original articles and patent documents.