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Presents a new wire bondable land grid array (LGA) chip scale package called NuCSP. NuCSP is a minimized body size wire bondable package with rigid substrate interposer. The design concept is to utilize the plating bars on the edges of the package substrate as the wire bond fingers. Bond fingers are redistributed inward to an array of plated through hole vias underneath the chip, then are connected to copper pads on the bottom of the package. NuCSP package size is about equal to die size + 3 mm. Using conventional PCB substrate manufacturing with 4/4 mils routing width/space and wire bonding process, NuCSP offers a very low cost package suitable for memory chips and low pin count application specific IC (ASIC) applications. The other advantages are that the use of wirebonding allow NuCSP be applicable for die size, pad count and pitch variations. Because it is wire bondable, NuCSP may be as generic as plastic quad flat pack (PQFP), yet providing smaller body size, lower cost and smaller package electrical parasitic parameters.

Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations.

Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations.

Solder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling.

Very little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.

Because of growing demand for slim, thin and cheap handheld devices, reduced-volume solder interconnects like land grid array (LGA) are becoming attractive and popular choices over the traditional ball grid array (BGA) packages. This study aims to investigate the mechanical shock and impact reliability of various solder alloys and BGA/LGA interconnect configurations.

Therefore, this paper uses drop testing experiments and numerical finite element simulations to evaluate and compare the reliability performance of both LGA and BGA components when exposed to drop and impact loadings. Additionally, three common solder alloys, including 63Sn37Pb, SAC305 and Innolot, are discussed.

The results of this study showed that electronic packages’ drop and impact reliability is strongly driven by the solder configuration and the alloy type. Particularly, the combination of stiff solder alloy and shorter joint, LGA’s assembled with SAC305, results in highly improved drop reliability. Moreover, the BGA packages’ performance can be considerably enhanced by using ductile and compliant solder alloys, that is, 63Sn37Pb. Finally, this paper discussed the failure mode of the various solder configurations and used simulation results to explain the crack and failure situations.

In literature, there is a lack of published work on the drop and impact reliability evaluation and comparison of LGA and BGA solders. This paper provides quantitative analysis on the reliability of lead-based and lead-free solders when assembled with LGA and BGA interconnects.

This paper aims to investigate and compare the reliability performance of land grid array (LGA) and ball grid array (BGA) solders, as well as the SAC105 and 63Sn37Pb solder alloys, in vibration loading conditions.

Reliability tests were conducted using a sine dwell with resonance tracking vibration experiment. Finite element simulations were performed to help in understanding the observed failure trends.

Reliability results showed that the tin-lead solders out-perform lead-free solders in vibrations loading. Additionally, the LGA solder type could provide a better vibration reliability performance than BGA solders. Failure analysis results showed that in LGAs, the crack is initiated at the printed circuit board side and at the component side in BGAs. In both types, the crack is propagated throughout in the intermetallic compound layer.

In literature, there is a lack of published data in the comparison between LGA and BGA reliability performance in vibration loadings. This paper provides useful insights in the vibration reliability behavior of the two common solder joint types.

The purpose of this paper is to investigate the feasibility of using land grid array (LGA) solder joints as a second-level interconnection option in low-temperature co-fired ceramic (LTCC)/printed wiring board (PWB) assemblies for telecommunication applications. The characteristic behaviour of two commercial lead-free solder materials (Sn4Ag0.5Cu and Sn3Ag0.5Cu0.5In0.05Ni) in reflow processes and thermal cycling tests are also evaluated.

The effect of the reflow temperature profile on voiding in two lead-free solders in LTCC/PWB assemblies was investigated using X-ray and scanning electron microscopy (SEM) investigations. The test assemblies were fabricated and exposed to a temperature cycling test (TCT) in a 0-100°C or −40 to 125°C temperature range. Organic PWB material with a low coefficient of thermal expansion (CTE) was primarily used. In addition, to compare LGA assemblies with low and high global thermal mismatches, an LTCC module/FR-4 assembly was also fabricated and exposed to a TCT in a 0-100°C temperature range. The characteristic lifetime of the test assemblies was determined using DC resistance measurements. The failure mechanisms of the interconnections were verified using scanning acoustic microscopy, SEM and finite element (FE)-SEM investigations.

This work showed that the solderability of AgPt-metallized LTCC modules was poor, resulting in excessive voiding. This problem was avoided by using pre-tinned modules. In the test assemblies, the Sn4Ag0.5Cu joints had a lower void content and a higher characteristic lifetime compared with the Sn3Ag0.5Cu0.5In0.05Ni joints. Furthermore, it was observed that the Sn3Ag0.5Cu0.5In0.05Ni joints were more prone to fail along the interface between the Ag₃Sn layer and the solder matrix than were the Sn4Ag0.5Cu joints. It was assumed that the observed difference in the primary failure mechanisms resulted in the decreased lifetime duration of the SnAgCu-InNi/Arlon in both temperature cycling conditions.

The results proved that the solderability of both solders in AgPt-metallized modules in a typical surface mount technology process was poor; however, the solderability of the test modules can be notably enhanced with pre-tinned pads. This work also demonstrated the effect of the metallization/solder pair on the failure mechanisms and failure rate in LTCC/PWB assemblies with LGA joints; the work also proved in the TCT, over a temperature range of 0-100°C, that using the present LGA joints in LTCC/PWB assemblies with a high global thermal mismatch did not increase the lifetime duration of the joints to the preferred level (3,000 cycles), whereas the performance of these joints was adequate in assemblies with a low global thermal mismatch. Moreover, the results indicated that using the LGA joint configuration enhanced the reliability of the LTCC/PWB assemblies compared with similar assemblies with collapsible ball grid array solder spheres.

Because they offer many properties favourable for IC package construction, ceramics have been in widespread use as an electronic package material since the early 1960s. In recent years, with trends towards higher speed semiconductors generating up to 30‐40 watts power, packaging materials must possess excellent thermal, electrical and mechanical properties. Aluminium nitride, with a thermal conductivity of 170 W/m.K., high fracture strength and a thermal coefficient of expansion match with silicon, has been used to manufacture multilayer LGA (land grid array) packages for high performance applications. A 725 AIN LGA has been manufactured and its performance characteristics have been compared with those of an alumina (with copper/tungsten slug) packaging alternative. Because of the high thermal conductivity of aluminium nitride, all designs can be made in a cavity‐up configuration, resulting in significant package body size reduction. The area under the cavity can be used for increasing I/O number and a ground plane can be inserted under the cavity, reducing simultaneous switching noise. Aluminium nitride is particularly beneficial for flip‐chip interconnection. Its close TCE match to silicon eliminates the stress reduction requirement for die underfill.

A new solder‐bumped flip chip land grid array (LGA) chip scale package (CSP) called NuCSP is presented in this paper. NuCSP is a minimized body size package with a rigid substrate (interposer). The design concept is to utilize the interposer to redistribute the very fine pitch peripheral pads on the solder‐bumped chip to much larger pitch area‐array pads on the printed circuit board (PCB). Using conventional PCB substrate manufacturing processes, NuCSP offers a very low‐cost package suitable for memory chips and low pin‐count application‐specific ICs (ASICs). Also, NuCSP is surface mount technology (SMT) compatible and can be joined to the PCB with a 6‐mil (0.15mm) thick 63wt %Sn‐37% Pb solder paste.

The purpose of this paper is to describe the behavior of different lead-free solders (95.5Sn3.8Ag0.7Cu, i.e. SAC387 and Sn7In4.1Ag0.5Cu, i.e. SAC-In) in thermomechanically loaded non-collapsible ball grid array (BGA) joints of a low-temperature co-fired ceramic (LTCC) module. The validity of a modified Engelmaier’s model was tested to verify its capability to predict the characteristic lifetime of an LTCC module assembly implementable in field applications.

Five printed wiring board (PWB) assemblies, each carrying eight LTCC modules, were fabricated and exposed to a temperature cycling test over a −40 to 125°C temperature range to determine the characteristic lifetimes of interconnections in the LTCC module/PWB assemblies. The failure mechanisms of the test assemblies were verified using scanning acoustic microscopy, scanning electron microscopy (SEM) and field emission SEM investigation. A stress-dependent Engelmaier’s model, adjusted for plastic-core solder ball (PCSB) BGA structures, was used to predict the characteristic lifetimes of the assemblies.

Depending on the joint configuration, characteristic lifetimes of up to 1,920 cycles were achieved in the thermal cycling testing. The results showed that intergranular (creep) failures occurred primarily only in the joints containing Sn7In4.1Ag0.5Cu solder. Other primary failure mechanisms (mixed transgranular/intergranular, separation of the intermetallic compound/solder interface and cracking in the interface between the ceramic and metallization) were observed in the other joint configurations. The modified Engelmaier’s model was found to predict the lifetime of interconnections with good accuracy. The results confirmed the superiority of SAC-In solder over SAC in terms of reliability, and also proved that an air cavity structure of the module, which enhances its radio frequency (RF) performance, did not degrade the reliability of the second-level interconnections of the test assemblies.

This paper shows the superiority of SAC-In solder over SAC387 solder in terms of reliability and verifies the applicability of the modified Engelmaier’s model as an accurate lifetime prediction method for PCSB BGA structures for the presented LTCC packages for RF/microwave telecommunication applications.

The purpose of this paper is to describe the effect of indium alloying on the thermal fatigue endurance of Sn3.8Ag0.7Cu solder in low‐temperature co‐fired ceramic (LTCC) modules with land grid array (LGA) joints and the feasibility of using a recalibrated Engelmaier model to predict the lifetime of LGA joints as determined with a test assembly.

Test assemblies were fabricated and exposed to a temperature cycling test over a temperature range of −40‐125°C. Organic printed wiring board (PWB) material with a low coefficient of thermal expansion was used to reduce the global thermal mismatch of the assembly. The characteristic lifetime, θ, of the test assemblies was determined using direct current resistance measurements. The metallurgy and failure mechanisms of the interconnections were verified using scanning acoustic microscopy, an optical microscope with polarized light, and scanning electron microscopy/energy dispersive spectrometry (SEM/EDS) investigations. Lifetime predictions of the test assemblies were calculated using the recalibrated Engelmaier model.

This work showed that indium alloying increased the characteristic lifetime of LGA joints by 15 percent compared with Sn3.8Ag0.7Cu joints. SEM/EDS analysis showed that alloying changed the composition, size, and distribution of intermetallic compounds within the solder matrix. It was also observed that a solid‐state phase transformation (Cu,Ni)₆Sn₅(→ (Ni,Cu)₃Sn₄ occurred at the Ni/(Cu,Ni)₆Sn₅ interface. Moreover, the results pointed out that individual recalibration curves for ceramic package/PWB assemblies with high (≥ 10 ppm/°C) and low (≈ 3‐4 ppm/°C) global thermal mismatches and different package thicknesses should be determined before the lifetime of LGA‐type assemblies can be predicted accurately using the recalibrated Engelmaier model.

The results proved that indium alloying of LGA joints can be done using In‐containing solder on pre‐tinned pads of an LTCC module, despite the different liquidus temperatures of the In‐containing and Sn3.8Ag0.7Cu solders. The characteristic metallurgical features and enhanced thermal fatigue endurance of the In‐alloyed SnAgCu joints were also determined. Finally, this work demonstrated the problems that exist in predicting the lifetime of ceramic packages with LGA joints using analytical modeling, and proposals for developing the recalibrated Engelmaier model to achieve more accurate results with different ceramic packages/PWB assemblies are given.