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1 – 2 of 2Divya Madhuri Badugu, Sunithamani S., Javid Basha Shaik and Ramesh Kumar Vobulapuram
The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).
Abstract
Purpose
The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).
Design/methodology/approach
To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset.
Findings
To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions.
Originality/value
The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.
Details
Keywords
Ramesh Kumar Vobulapuram, Javid Basha Shaik, Venkatramana P., Durga Prasad Mekala and Ujwala Lingayath
The purpose of this paper is to design novel tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs).
Abstract
Purpose
The purpose of this paper is to design novel tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs).
Design/methodology/approach
To design the proposed TFET, the bilayer GNRs (BLGNRs) have been used as the channel material. The BLGNR-TFET is designed in QuantumATK, depending on 2-D Poisson’s equation and non-equilibrium Green’s function (NEGF) formalism.
Findings
The performance of the proposed BLGNR-TFET is investigated in terms of current and voltage (I-V) characteristics and transconductance. Moreover, the proposed device performance is compared with the monolayer GNR-TFET (MLGNR-TFET). From the simulation results, it is investigated that the BLGNR-TFET shows high current and gain over the MLGNR-TFET.
Originality/value
This paper presents a new technique to design GNR-based TFET for future low power very large-scale integration (VLSI) devices.
Details