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The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).

To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset.

To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions.

The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

The purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.

In the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.

The effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.

This paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

Delay and power dissipation are the two major design constraints in very large scale integration (VLSI) circuits. These arise due to millions of active devices and interconnections connecting this gigantic number of devices on the chip. Important technique of repeater insertion in long interconnections to reduce delay in VLSI circuits has been reported during the last two decades. This paper deals with delay, power dissipation and the role of voltage‐scaling in repeaters loaded long interconnects in VLSI circuits for low power environment.

Trade off between delay and power dissipation in repeaters inserted long interconnects has been reviewed here with a bibliographic survey. SPICE simulations have been used to validate the findings.

Optimum number of uniform sized CMOS repeaters inserted in long interconnects, lead to delay minimization. Voltage‐scaling is highly effective in reduction of power dissipation in repeaters loaded long interconnects. The new finding given here is that optimum number of repeaters required for delay minimization decreases with voltage‐scaling. This leads to area and further power saving.

The bibliographic survey needs to be revised in future, taking the various other aspects of VLSI interconnects viz. noise, cross talk extra into account.

The paper is of high significance in VLSI design and low‐power high‐speed applications. It is also valuable for new researchers in this emerging field.

Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).

This paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.

This paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.

This paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.

This paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

The performance of a high‐speed chip is highly dependent on the interconnects, which connect different macro cells within a VLSI chip. Delay, power dissipation and cross‐talk are the major design constraints for high performance VLSI interconnects. The importance of on‐chip inductance is continuously increasing with higher clock frequency, faster on‐chip rise time, wider wires, ever‐growing length of interconnects and introduction of new materials for low resistance interconnects. In the current scenario, interconnect is modeled as an RLC transmission line. Interconnect width optimization plays an important role in deciding transition delay and power dissipation. This paper aims to optimize interconnect width for a matched condition to reduce power and delay parameters.

Width optimization is done for two sets of interconnect terminating conditions, namely active gate and passive capacitance. SPICE simulations have been used to validate the findings.

For a driver interconnect load model terminated by an active gate load, a trade‐off exists between short circuit and dynamic power in inductive interconnects, since with wider lines dynamic power increases, but short circuit power of the load gate decreases due to reduced transient delay. Whereas, for a line terminated by a capacitor, such trade‐off does not exist. Many of the previous researches have modeled the active gate load at the terminating end by its input parasitic gate capacitance.

This paper shows that such modeling leads to inaccuracy in estimation of power, and therefore non‐optimal width selection, especially for large fan‐out conditions.

The finding is that the impedance matching between transmission line at driver and load ends plays an important role in estimation of overall power dissipation and transition delay of a VLSI circuit.

This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-V_t technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm.

Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-V_t transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control.

An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (V_t) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes.

Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.

A major limitation to achieving significant speed increases in VLSI lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of fifth generation supercomputing, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information between chips or between boards. As the on‐chip performance of VLSI continues to improve via the scale‐down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realised in reducing cross‐talk between the metallic routings, and the interconnects need no longer be constrained to the plane of the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

To review and explore optical fiber and carbon nanotube (CNT) as prospective alternatives to copper in VLSI interconnections.

As the technology moves to deep submicron level, the interconnect width also scales down. Increasing resistivity of copper with scaling and rising demands on current density drives the need for identifying new wiring solutions. This paper explores various alternatives to copper. Metallic CNTs, optical interconnects are promising candidates that can potentially address the challenges faced by copper.

Although, the theoretical aspects proves CNTs and optical interconnect to be better alternative against copper on the ground of performance parameters such as power dissipation, switching delay, crosstalk. But copper would last for coming decades on integration basis.

This paper reviews the state‐of‐the‐art in CNT interconnect and optical interconnect research; and discusses both the advantages and challenges of these emerging technologies.

The purpose of this paper is to explore and evaluate the performance comparison of carbon nanotubes (CNT) and nickel silicide (NiSi) nanowires interconnects as prospective alternatives to copper wire interconnects.

The increasing resistivity of the copper wire with scaling and rising demands on current density drives the need for identifying new wiring solutions. This paper explores the various alternatives to copper. The metallic bundle CNTs and NiSi nanowires are promising candidates that can potentially address the challenges faced by copper. This paper analyzes various electrical models of carbon nanotube and recently introduced novel interconnect solution using NiSi nanowires.

The theoretical studies proves CNTs and NiSi nanowires to be better alternatives against copper on the ground of performance parameters, such as effective current density, delay and power consumption. NiSi nanowire provides highest propagation speed for short wire length, and copper is the best for intermediate wire length, while bundle CNTs is faster for long wire length. NiSi nanowire has lowest power consumption than copper and CNTs.

This paper investigates, assess and compares the performance of carbon nanotubes (CNT) and NiSi nanowires interconnects as prospective alternatives to copper wire interconnects in future VLSI chips.

This paper aims to present the edge scattering dominant circuit modeling. The effect of crosstalk on gate oxide reliability (GOR), along with the mitigation using shielding technique is further studied.

An equivalent distributed Resistance Inductance Capacitance circuit of capacitively coupled interconnects of multilayer graphene nanoribbon (MLGNR) has been considered for T Simulation Program with Integrated Circuit Emphasis (TSPICE) simulations under functional and dynamic switching conditions. Complementary metal oxide semiconductor driver transistors are modeled by high performance predictive technology model that drive the distributed segment with a capacitive load of 0.001 fF, V_DD and clock frequency as 0.7 V and 0.2 GHz, respectively, at 14 nm technology node.

The results reveal that the crosstalk induced delay and noise area are dominated by the overall mean free path (MFP) (i.e. including the effect of edge roughness induced scattering), in contrary to, acoustic and optical scattering limited MFP with the temperature, width and length variations. Further, GOR, estimated in terms of average failure rate (AFR), shows that the shielding technique is an effective method to minimize the relative GOR failure rate by, 0.93e-7 and 0.7e-7, in comparison to the non-shielded case with variations in interconnect’s length and width, respectively.

Considering realistic circuit modeling for MLGNR interconnects by incorporating the edge roughness induced scattering mechanism, the outcomes exhibit more penalty in terms of crosstalk induced noise area and delay. The shielding technique is found to be an effective mitigating technique for minimizing AFR in coupled MLGNR interconnects.