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An exact analysis is presented for the creep deformation of solder interconnects subjected to the actions of bending moment, twisting moment and axial force. Dimensionless interaction curves and charts which relate the variables, interconnect geometry, solder material properties, axial force, bending moment, twisting moment, bending stress, shearing stress, curvature rate and twist rate are also provided for engineering practice convenience. The constitutive relationship of the 96.5Sn3.5Ag solder interconnects is described by the Garofalo‐Arrhenius steady‐state creep equation.

A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is presented. Emphasis is placed on a new understanding of the key elements (for example, tapes, bumps, inner lead bonding, testing and burn‐in on tape‐with‐chip, encapsulation, outer lead bonding, thermal management, reliability and rework) of this rapidly moving technology.

The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.

This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.

A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high‐power chips on top and low‐power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to “dig” holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (>99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin‐wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high‐power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper‐filled TSV interposer and the high‐ and low‐power chips are recommended to reduce creep damage of the lead‐free microbump solder joints and prolong their lives.

The paper's findings will be very useful to the electronic industry.

The reliability of 0·5 mm pitch, 208‐pin FQFP solder joints has been studied by experimental temperature cycling and 3‐D nonlinear finite element analysis. Temperature cycling results have been presented as a Weibull distribution. Thermal fatigue life of the solder joints has been estimated based on the calculated plastic strain and isothermal fatigue data on solders. A correlation between the experimental and analytical results has also been made.

The reliability of 0.5 mm pitch, 32‐pin thin small outline package (TSOP) solder joints has been studied by experimental temperature cycling and a cost‐effective 3‐D non‐linear finite element analysis. Temperature cycling results have been presented as a Weibull distribution, and an acceleration factor has been established for predicting the failure rate at operating conditions. Thermal fatigue life of the corner solder joints has been estimated based on the calculated plastic strain, Coffin‐Manson law and isothermal fatigue data on solders. A correlation between the experimental and analytical results has also been made. Furthermore, failure analysis of the solder joints has been performed using scanning electron microscopy (SEM) and an optical method. Finally, a quantitative comparison between the Type‐I and Type‐II TSOP solder joints has been presented.

The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed.

Lead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process.

With the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed.

This literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process.

The unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.

In this study, the reliability of solder joints and plated‐through hole copper pads/barrels of pin grid array assemblies under rework condition has been determined by fatigue experiments. The cross‐sections of the re‐worked PGA assemblies (before and after fatigue tests) are also provided for a better understanding of the failure mechanisms of the composite structure. Furthermore, the load‐drop curves of the PGA interconnects for up to three reworks are provided for a better estimate of their fatigue life.

The reliability of 0.4 mm pitch, 28 mm body size, 256‐pin plastic quad flat pack (QFP) no‐clean and water‐clean solder joints has been studied by temperature cycling and analytical analysis. The temperature cycling test was run non‐stop for more than 6 months, and the results have been presented as a Weibull distribution. A unique temperature cycling profile has been developed based on the calculated lead stiffness, elastic and creep strains in the solder joint, and solder data. Also, the thermal fatigue life of the solder joints has been estimated and correlated with experimental results. Furthermore, a failure analysis of the solder joints has been performed using scanning electron microscopy (SEM). Finally, a quantitative comparison between the no‐clean and water‐clean QFP solder joints has been presented.

Several finite element models were proposed to investigate the effects of voids and their interactions on SMT solder joint reliability in thermal mismatch loading. Both linear elastic analysis and non‐linear and time‐dependent finite element analysis were performed on models with different sizes and locations of voids in solder joints. The focus was on the interactions of the two voids. Various distances between voids are considered. Constitutive equations accounting for both plasticity and creep for one solder material were assumed and implemented in a finite element program. The following observations have been obtained: (i) the stress and strain in a solder joint of two voids are different from those of a one void joint; (ii) the stress and strain reach a maximum for a particular void size and location either along the interface of the solder joint or at the edges of voids; (iii) the initiation of interfacial debonding may be induced by the interaction of the voids; (iv) creep due to thermal cycling has a significant effect on solder joint reliability.