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The aim of the research was to find a structure of the power electronics controlled current source with extended pass band, which would better match a source output current within an input (reference) signal. Also, pulse modulation components in output current of current source should be minimized.

The power electronics controlled current source utilizes both, the concept of the inductor with variable (controlled) inductance located at the output of an inverter and the concept of the multi‐channel (interleaved) inverter. The small signal (linear) and simulation models of an active filter have been investigated.

The work presents the concept of 1‐phase active shunt filter with utilization of the power electronics current source about extended pass‐band.

The research should be continued to achieve stability of the electrical system with variable parameters of the power network and receiver.

The research will be continued towards realization of a laboratory model of a 3‐phase active shunt filter with the DSP based control module.

Social implications are difficult to determine.

The paper presents a new concept of the precision power electronics controlled current source with the extended pass‐band. The controlled current source is the fundamental block of a power electronics active shunt filter.

The purpose of this paper is to design a voltage reference circuit for current source of radio frequency integrated circuit blocks. The voltage reference circuit is called voltage for current source (VCS).

The circuit concept is discussed. A voltage‐controlled oscillator (VCO) and buffer circuit together with VCS circuit are built to prove the concept. Though the VCS circuit employs no array of diode like standard bandgap circuit, it still employs the concept of proportional to absolute temperature (PTAT) and a complement to absolute temperature (CTAT) elements. The integrated VCO, together with VCO core and VCO buffer circuits, are designed for W‐CDMA application particularly for the demodulator section. All circuits are built in f_T=45 GHz SiGe BiCMOS process.

At 760 MHz the power consumption for core circuit is 0.6 and 3.3 mA for VCO buffer amplifier. The fabricated VCO circuit together with VCO buffer was tested and measured with VCO output of −6 dBm at 760 MHz with variation of 0.1 dBm across −40°C to 85°C.

A voltage reference circuit which is derived from PTAT and CTAT current generators is presented. The circuit is capable of providing a constant current across absolute temperature or a current PTAT.

Presents a system capable of achieving optimal compensation (in real time) by elimination of differential current and employing power electronic controlled current sources. The functional block diagram and a description of the working principle are included. Simulation tests were carried out on current source and active compensation system. The results of simulation and experimental tests of prototype model of controlled current source and compensator confirm a considerable reduction of source current distortion at strong distortions of voltage and current of receiver, a fast response to step changes of load and good stability of its work.

This paper aims to present a method for the efficient reduction of networks modelling parasitic couplings in very‐large‐scale integration (VLSI) circuits.

The parasitic effects are modelled by large RLC networks and current sources for the digital switching currents. Based on the determined behaviour of the digital modules, an efficient description of these networks is proposed, which allows for a more efficient model reduction than standard methods.

The proposed method enables a fast and efficient simulation of the parasitic effects. Additionally, an extension of the reduction method to elements, which incorporate some supply voltage dependence to model the internal currents more precisely than independent current sources is presented.

The presented method can be applied to large electrical networks, used in the modelling of parasitic effects, for reducing their size. A reduced model is created which can be used in investigations with circuit simulators requiring a lowered computational effort.

Contrary to existing methods, the presented method includes the knowledge of the behaviour of the sources in the model to enhance the model reduction process.

This paper aims to clarify voltage sourced converter’s (VSC’s) influence rules on the alternating current (AC) short-circuit current and identify the key factors, so as to propose the short-circuit current suppression strategy.

This paper investigates the key factors which impact the short-circuit current supplied by the VSC based on the equivalent current source model. This study shows that the phase of the VSC equivalent current source is mainly affected by the type of fault, whereas the amplitude is mainly decided by the control mode, the amplitude limiter and the electrical distance. Based on the above influence mechanism, the dynamic limiter with short-circuit current limiting function is designed. The theoretical analysis is verified by simulations on PSCAD.

The short-circuit current feeding from VSC is closely related to the control mode and control parameters of the VSC, fault type at AC side and the electrical distance of the fault point. The proposed dynamic limiter can make VSC absorb more reactive power to suppress the short-circuit current.

The dynamic limiter proposed in this paper is limited to suppress three-phase short-circuit fault current. The future work will focus more on improving and extending the dynamic limiter to the fault current suppression application in other fault scenarios.

The research results provide a reference for the design of protection system.

The key influence factors are conducive to put forward the measures to suppress the fault current, eliminate the risk of short-circuit current exceeding the standard and reduce the difficulty of protection design.

This paper aims to present an inverter with a current-source input for 400 Hz avionic systems to have a system which removes DC-link capacitors and presents a high efficiency.

A battery-powered DC link inductor generates a constant-current source. A single high-frequency switch is used to provide a sinusoidally modulated current before the inverter. The output of the switch is “unfolded” by a thyristor-based H-bridge inverter to generate an AC output current. The system uses a CL low-pass filter to obtain a 400 Hz pure sine wave by removing pulse width modulation components.

Simulations and Typhoon HIL real-time experiments were performed with closed-loop control to validate the proposed inverter concept while meeting the critical standards of MIL-STD-704F.

This current source inverter topology is suitable for avionic systems that require 400 Hz output frequency. The topology uses small DC-link inductor and eliminates bulky capacitor which determines the inverter lifetime.

The purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures.

The conventional DAC topology performance tends to degrade at high-resolution applications. A hybrid topology, which combines an equal number of bits of thermometer coding and binary-weighted resistor architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V.

Measured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input range of 0.9 V at the clock rate of 200 MHz, and this DAC was proven monotonic. This 0.068 mm² DAC consumed 12.6 mW for the data conversion.

This paper is of value in showing the equal division of bits from thermometer coding and binary-weighted resistor architectures provides smaller die size and enhances the performance of hybrid DAC, in terms of linearity, which are DNL and INL errors and guarantees monotonicity at higher sampling frequency.

This paper aims to design the circuit for electromagnetic interface (EMI) reduction in liquid crystal display (LCD).

The cascode level shifter and segmented driver circuit are applied in LCD column driver integrated circuit (IC) for EMI reduction. Cascode current mirror is used in the proposed level shifter for DC voltage biasing and reduction of the driving current which passes through the level shifter. The on-off switching currents and transient times are measured and compared between the conventional and proposed level shifters. Additionally, a segmented data latch is obtained by the timing spread solution in data latch, and applied to split the large peak switching current into a number of smaller peak current. The timing spread-operation does not actually reduce the total power of the noise, instead, it spreads the noise power evenly over the frequency bandwidth. The optimal number of latch is dependent on the operating frequency and EMI allowance. The column driver IC and clock controller are integrated in 0.18 μm CMOS technology with 1-poly and 4-metal process.

The post-layout simulation shows that the proposed column driver circuit for LCD driver IC significantly reduces the peak switching current, and it results in the reduction of EMI noise level by more than 15 dB. It is obtained with 20 segmented operations in data latch at 40 MHz frequency.

The advantage of the cascode current source is that it can provide a well-controlled bias current with an accurate current transfer ratio. To reduce the EMI noise in LCD driver circuit, the cascode current source is properly located for the DC bias block in the level shifter. The application is rarely done by others, and a significant EMI noise reduction is found. The well-controlled current source provides a high performance switching in the level shifter.

The purpose of this paper is to introduce a low power digital‐to‐analog converter (DAC) by using a sequential triggering technique in cascaded current source.

The block of current cell consists of current switch and source. A sequential switching on process is implemented with the current triggering technique in source. An experiment of 12‐b 150‐MS/s DAC has been integrated in a single‐poly four‐metal 0.35 μm CMOS process.

Compared with conventional cell array in 12‐b 150‐MS/s DAC, the proposed cell array shows that more than 30 percent of power consumption is reduced in full digital bit operation with allowable linearity error of 0.4 LSB.

This paper presents a new operation method of cell array in a current‐steering digital‐to‐analog converter (DAC) to reduce the power consumption significantly.

The purpose of this paper is to detect the source of stray current interference on underground pipelines in urban areas using a joint time/frequency method of signal analysis.

Investigations are performed on an underground pipeline located in the vicinity of the two direct current tractions: a tramway line and a train line. The results of the analysis are presented in the form of spectrograms, which illustrate changes in the spectral power density of the potential of the rails and of the potential of the pipe in the joint domain time‐frequency.

The comparison of the spectrograms can be used to evaluate if and which stray current source has influence on the investigated metal construction.

The combined analysis in the domain of time and frequency can be used as a supplementary one providing new information useful in the evaluation of stray current corrosion hazard. In the presence of several electric field sources in urban areas, this method reveals the complete time‐frequency characteristic of each stray current source and its interference on the investigated construction.