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The purpose of this paper is to propose an analytical model for estimating propagation delay in coupled resistance-inductance-capacitance (RLC) interconnects.

With higher frequency of operation, longer length of interconnect and fast transition time of the signal, the resistor capacitor (RC) models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are required. In this paper, an analytical model for estimation of interconnect delay is developed for simultaneously switching lines. Two distributed RLC lines coupled inductively and capacitively are considered. To validate the proposed model, SPICE results are compared with the proposed analytical results. Each line in the coupled structure is terminated by a capacitive load of 30fF. The driving signal is considered symmetrical with equal rise and fall time of 5 ps and OFF/ON time of 45 ps. The model is validated for both in-phase and out of phase switching of lines.

It is observed that the model works well for both the phases of inputs switching. The derived expressions of delay exhibit complete physical insight, and the results obtained are in excellent agreement with SPICE results. Comparison of analytical delay with SPICE delay shows an average error of < 2.7 per cent.

The analytical expressions for interconnect delay are derived for the first time under simultaneously switching scenario. This model is useful to estimate delay across the inductively and capacitively coupled interconnects.

The aim of this paper is to analyze the effects of aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of a coupled VLSI‐interconnect system.

Signal delay, power dissipation and crosstalk noise in interconnect can be influenced by variation in load of another interconnect which is coupled to it. For active gate and passive capacitive load variations, such effects are studied through SPICE simulations of a coupled interconnect pair in a 0.13 μm technology. Crosstalk between a coupled pair, is affected by transition time of the coupled signal, interconnect length, distance between interconnects, size of driver and receiver, pattern of input, direction of flow of signal and clock skew. In this work, influence of an aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of delay, power consumption and crosstalk in a victim‐line of a coupled VLSI‐interconnect system are determined through SPICE simulation. In this experiment, the victim line is terminated by a fixed capacitive load and the coupled to aggressor line has variable load, either passive capacitive or active gate. Four different input signal cases have been considered for the two types of variable load. Distributed RLC transmission model of interconnect is considered for the SPICE simulations.

The simulation results reveal that the effects are much dependent on the type of load and signal variations at the inputs of the two mutually coupled interconnects. Load control at the aggressor far end can be used to minimize some of the adverse effects of crosstalk.

This paper shows that in interconnect, signal delay, power consumption and crosstalk are all affected by load variations in a coupled neighboring interconnect.

This paper aims to present the simulation, fabrication and testing of a novel ultra-wide band (UWB) band-pass filters (BPFs) with better transmission and rejection characteristics on a low-loss Taconic substrate and analyze using the coupled theory of resonators for UWB range covering L, S, C and X bands for radars, global positioning system (GPS) and satellite communication applications.

The filter is designed with a bent coupled transmission line on the top copper layer. Defected ground structures (DGSs) like complementary split ring resonators (CSRRs), V-shaped resonators, rectangular slots and quad circle slots (positioned inwards and outwards) are etched in the ground layer of the filter. The circular orientation of V-shaped resonators adds compactness when linearly placed. By arranging the quad circle slots outwards and inwards at the corner and core of the ground plane, respectively, two filters (Filters I and II) are designed, fabricated and measured. These two filters feature a quasi-elliptic response with transmission zeros (TZs) on either side of the bandpass response, making it highly selective and reflection poles (RPs), resulting in a low-loss filter response. The transmission line model and coupled line theory are implemented to analyze the proposed filters.

Two filters by placing the quad circle slots outwards (Filter I) and inwards (Filter II) were designed, fabricated and tested. The fabricated model (Filter I) provides transmission with a maximum insertion loss of 2.65 dB from 1.5 GHz to 9.2 GHz. Four TZs and five RPs are observed in the frequency response. The lower and upper stopband band width (BW) of the measured Filter I are 1.2 GHz and 5.5 GHz of upper stopband BW with rejection level greater than 10 dB, respectively. Filter II (inward quad circle slots) operates from 1.4 GHz to 9.05 GHz with 1.65 dB maximum insertion loss inside the passband with four TZs and four RPs, which, in turn, enhances the filter characteristics in terms of selectivity, flatness and stopband. Moreover, 1 GHz BW of lower and upper stopbands are observed. Thus, the fabricated filters (Filters I and II) are therefore evaluated, and the outcomes show good agreement with the electromagnetic simulation response.

The limitation of this work is the back radiation caused by DGS, which can be eradicated by placing the filter in the cavity and retaining its performance.

The proposed UWB BPFs with novel resonators find their role in the UWB range covering L, S, C and X bands for radars, GPS and satellite communication applications.

To the best of the authors’ knowledge, for the first time, the authors develop a compact UWB BPFs (Filters I and II) with BW greater than 7.5 GHz by combining reformed coupled lines and DGS resonators (CSRRs, V-shaped resonators [modified hairpin resonators], rectangular slots and quad circle slots [inwards and outwards]) for radars, GPS and satellite communication applications.

The purpose of this paper is to present a broadband parallel coupled‐line quadrature coupler implemented with lumped‐elements.

The even‐ and odd‐mode method is used to compute the proposed coupler, and the analysis and optimization are done using the computer‐aided design tools. A design example of a broadband tunable quadrature coupler is provided.

This novel structure is clearly increasing the conductor spacing and decreasing the whole structure size, at the same time, the bandwidth is much wider.

This paper shows how a parallel coupled‐line quadrature coupler with lumped‐elements has been analyzed and designed, and proposes a simple and convenient method to calculate this structure. Compared with the normal parallel coupled‐line structure, the conductor spacing of this coupler is increased effectively, while the structure size is decreased. In addition, because of the tunable embedded capacitors, the bandwidth becomes much wider – a broadband up to 77 percent is achieved.

To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay.

Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 μm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size W_n=3.9 μm and W_p=7.8 μm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. V_A switching from low to high; input to line B, i.e. V_B switching from low to high; input to line A i.e V_A switching from low to high; input to line B, i.e. V_B switching from high to low; V_A switching from high to low and V_B at static low; V_A switching from high to low and V_B at static high.

This paper shows the prominent factors such as edge rate, length and pattern of inputs affecting the noise. It is observed that presence of inductive effects can seriously hamper the functioning of the chip. This paper further reveals that repeater insertion not only reduces the propagation delay but also crosstalk levels for coupled lines. Repeaters can be efficiently utilized for reduction of propagation delay and crosstalk noise at a trade of marginal increase in power dissipation. The power‐delay‐crosstalk‐product (PDCP) criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Based on PDCP a reduction in crosstalk of about 60 times and delay of 4.2 percent is achieved at trade of 13.2 percent increase in power dissipation in comparison to PDP.

The PDCP criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Instead of PDP criterion, PDCP criterion is best suited for determination of optimum number of repeaters for overall minimization of delay, power and crosstalk.

The purpose of this paper is to design a suitable guard trace to reduce the electromagentic interference between two closely spaced high frequency transmission lines. A novel cross-shaped resonator combined via fence is passed down to alleviate far-end and near-end crosstalk (NEXT) in tightly coupled high-speed transmission lines. The distance between the adjacent transmission lines is increased stepwise as a function of trace width.

A rectangular-shaped resonator via fence is connected by a guard trace has been proposed to overcome the coupling between the traces that is separated by 2 W. Similarly, by creating a cross-shaped resonator via fence connected by guard trace that reduces the spacing further by 1.5 W.

A tightly coupled transmission line structure that needs separation by a designed unit cell structure. Further research needs to be conducted to improve the NEXT, far-end crosstalk (FEXT) and spacing between the transmission lines.

This study portrays a novel method that combines the resonators via fence with a minimum spacing between the tightly coupled transmission lines which reduce the NEXT and FEXT; thereby reducing the size of the routing area. The resultant test structures are characterized at high frequencies using time domain and frequency domain analysis. The following scattering parameters such as insertion loss, NEXT and FEXT of the proposed method are measured as 1.504 dB, >30 dB and >20 dB, respectively.

This paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects.

The paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μm, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μm, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances (R=0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μm. The corresponding NMOS width is half of PMOS width.

It is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver.

While designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay.

The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node.

This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out.

The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.

This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method.

The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed.

The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage.

Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab.

The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.

As the speed, density, power dissipation, and overall performance of semiconductor chips continue to improve, electronic equipment designers are finding that their ability to utilise new, high performance ICs is limited by the electrical performance, cost and turnaround time associated with the higher levels of packaging and interconnection. With the evolution of silicon foundries, CAD systems, logic array and standard cell technology, the designer now has the ability to develop and implement custom IC functions rapidly at a fraction of the cost and time associated with full custom IC development. The driving force for this evolution is the need for reduction of product development time and cost. As electronic product life cycles continue to decrease, so must the development time. Although the need to reduce component development times has been acted on first by the semiconductor manufacturers, suppliers of packaging and interconnection components are also feeling the need to provide customised designs rapidly and at low cost. Unilayer II is a discrete wire circuit board technology with a wiring density capability approximating that of multilayer printed wiring boards. However, since the wiring is defined in software and implemented on a numerically controlled wiring machine, the time and cost associated with development, and also with wiring changes, is greatly reduced. This paper presents the results of extensive electrical testing performed to characterise the electrical performance of the discrete wire Unilayer II transmission lines. Characteristic impedance, propagation velocity, capacitance, inductance, and crosstalk are discussed in detail.