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This paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects.

The paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μm, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μm, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances (R=0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μm. The corresponding NMOS width is half of PMOS width.

It is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver.

While designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method.

The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed.

The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage.

Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab.

The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.

To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay.

Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 μm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size W_n=3.9 μm and W_p=7.8 μm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. V_A switching from low to high; input to line B, i.e. V_B switching from low to high; input to line A i.e V_A switching from low to high; input to line B, i.e. V_B switching from high to low; V_A switching from high to low and V_B at static low; V_A switching from high to low and V_B at static high.

This paper shows the prominent factors such as edge rate, length and pattern of inputs affecting the noise. It is observed that presence of inductive effects can seriously hamper the functioning of the chip. This paper further reveals that repeater insertion not only reduces the propagation delay but also crosstalk levels for coupled lines. Repeaters can be efficiently utilized for reduction of propagation delay and crosstalk noise at a trade of marginal increase in power dissipation. The power‐delay‐crosstalk‐product (PDCP) criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Based on PDCP a reduction in crosstalk of about 60 times and delay of 4.2 percent is achieved at trade of 13.2 percent increase in power dissipation in comparison to PDP.

The PDCP criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Instead of PDP criterion, PDCP criterion is best suited for determination of optimum number of repeaters for overall minimization of delay, power and crosstalk.

The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay.

The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node.

This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out.

The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.

This paper aims to present the edge scattering dominant circuit modeling. The effect of crosstalk on gate oxide reliability (GOR), along with the mitigation using shielding technique is further studied.

An equivalent distributed Resistance Inductance Capacitance circuit of capacitively coupled interconnects of multilayer graphene nanoribbon (MLGNR) has been considered for T Simulation Program with Integrated Circuit Emphasis (TSPICE) simulations under functional and dynamic switching conditions. Complementary metal oxide semiconductor driver transistors are modeled by high performance predictive technology model that drive the distributed segment with a capacitive load of 0.001 fF, V_DD and clock frequency as 0.7 V and 0.2 GHz, respectively, at 14 nm technology node.

The results reveal that the crosstalk induced delay and noise area are dominated by the overall mean free path (MFP) (i.e. including the effect of edge roughness induced scattering), in contrary to, acoustic and optical scattering limited MFP with the temperature, width and length variations. Further, GOR, estimated in terms of average failure rate (AFR), shows that the shielding technique is an effective method to minimize the relative GOR failure rate by, 0.93e-7 and 0.7e-7, in comparison to the non-shielded case with variations in interconnect’s length and width, respectively.

Considering realistic circuit modeling for MLGNR interconnects by incorporating the edge roughness induced scattering mechanism, the outcomes exhibit more penalty in terms of crosstalk induced noise area and delay. The shielding technique is found to be an effective mitigating technique for minimizing AFR in coupled MLGNR interconnects.

To analyze the effect of voltage scaling on crosstalk.

Voltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus, a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product. Therefore, their lies an optimized supply voltage where‐in power dissipation and propagation delay can be optimized. Many of the previous researches have discussed about power dissipation and propagation delay only with voltage scaling. This paper for first time shows the effect on crosstalk in voltage scaled interconnects. In this paper, we primarily study the noise for an input signal having transition time of 50 ps. The simulations are run for interconnect length of 2 and 4 mm. These parameters are varied for four different cases of stimulations to aggressor and victim lines viz. V_A (input at aggressor node A) and V_B (input at victim node B) switching in same direction; V_A is switching and V_B at static low; V_A and V_B are switching in opposite direction; V_A is switching and V_B at static high.

It is quite encouraging to observe that irrespective of interconnect length and technology node used, an optimized voltage scaling reduces normalized crosstalk level.

Voltage scaling can be effectively used for crosstalk reduction by the new era VLSI interconnect designers. This paper shows simulation results for crosstalk reduction in different nano‐sized CMOS driven RLC‐modeled interconnects.

Fixed mode noise and random mode noise always exist in the image sensor, which affects the imaging quality of the image sensor. The charge diffusion and color mixing between pixels in the photoelectric conversion process belong to fixed mode noise. This study aims to improve the image sensor imaging quality by processing the fixed mode noise.

Through an iterative training of an ergoable long- and short-term memory recurrent neural network model, the authors obtain a neural network model able to compensate for image noise crosstalk. To overcome the lack of differences in the same color pixels on each template of the image sensor under flat-field light, the data before and after compensation were used as a new data set to further train the neural network iteratively.

The comparison of the images compensated by the two sets of neural network models shows that the gray value distribution is more concentrated and uniform. The middle and high frequency components in the spatial spectrum are all increased, indicating that the compensated image edges change faster and are more detailed (Hinton and Salakhutdinov, 2006; LeCun et al., 1998; Mohanty et al., 2016; Zang et al., 2023).

In this paper, the authors use the iterative learning color image pixel crosstalk compensation method to effectively alleviate the incomplete color mixing problem caused by the insufficient filter rate and the electric crosstalk problem caused by the lateral diffusion of the optical charge caused by the adjacent pixel potential trap.

As the speed, density, power dissipation, and overall performance of semiconductor chips continue to improve, electronic equipment designers are finding that their ability to utilise new, high performance ICs is limited by the electrical performance, cost and turnaround time associated with the higher levels of packaging and interconnection. With the evolution of silicon foundries, CAD systems, logic array and standard cell technology, the designer now has the ability to develop and implement custom IC functions rapidly at a fraction of the cost and time associated with full custom IC development. The driving force for this evolution is the need for reduction of product development time and cost. As electronic product life cycles continue to decrease, so must the development time. Although the need to reduce component development times has been acted on first by the semiconductor manufacturers, suppliers of packaging and interconnection components are also feeling the need to provide customised designs rapidly and at low cost. Unilayer II is a discrete wire circuit board technology with a wiring density capability approximating that of multilayer printed wiring boards. However, since the wiring is defined in software and implemented on a numerically controlled wiring machine, the time and cost associated with development, and also with wiring changes, is greatly reduced. This paper presents the results of extensive electrical testing performed to characterise the electrical performance of the discrete wire Unilayer II transmission lines. Characteristic impedance, propagation velocity, capacitance, inductance, and crosstalk are discussed in detail.

An experiment was conducted to examine the effect of post‐reflow no‐clean solder paste residue on near‐end and far‐end signal crosstalk due to changes in dielectric constant and leakage resistance in the circuit environment. Additionally, the effect of different frequency levels on post‐reflow residue was examined. Data from these studies are presented in this paper.

The aim of this paper is to analyze the effects of aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of a coupled VLSI‐interconnect system.

Signal delay, power dissipation and crosstalk noise in interconnect can be influenced by variation in load of another interconnect which is coupled to it. For active gate and passive capacitive load variations, such effects are studied through SPICE simulations of a coupled interconnect pair in a 0.13 μm technology. Crosstalk between a coupled pair, is affected by transition time of the coupled signal, interconnect length, distance between interconnects, size of driver and receiver, pattern of input, direction of flow of signal and clock skew. In this work, influence of an aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of delay, power consumption and crosstalk in a victim‐line of a coupled VLSI‐interconnect system are determined through SPICE simulation. In this experiment, the victim line is terminated by a fixed capacitive load and the coupled to aggressor line has variable load, either passive capacitive or active gate. Four different input signal cases have been considered for the two types of variable load. Distributed RLC transmission model of interconnect is considered for the SPICE simulations.

The simulation results reveal that the effects are much dependent on the type of load and signal variations at the inputs of the two mutually coupled interconnects. Load control at the aggressor far end can be used to minimize some of the adverse effects of crosstalk.

This paper shows that in interconnect, signal delay, power consumption and crosstalk are all affected by load variations in a coupled neighboring interconnect.