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The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay.

The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node.

This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out.

The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.

The purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.

In the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.

The effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.

This paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

Purpose of this study is to design a compact gap coupled anchor shape patch antenna for wireless local area network/high performance radio local area network and worldwide interoperability for microwave access applications.

An anchor shape microstrip antenna is conceived, designed, simulated and measured. The anchor shape antenna is transformed to its rectangular equivalent by conserving the patch area. Modeling and simulation of the antenna is performed by Ansys high frequency structure simulator (HFSS) electromagnetic solver based on the concept of finite element method. The simulated results are experimentally verified by using Agilent E5071C vector network analyzer. Theoretical analysis of an electromagnetically gap coupled anchor shape microstrip patch antenna has been performed by obtaining the lumped element equivalent of the transformed antenna.

The proposed antenna has a compact conducting patch of dimension 0.26λ × 0.12λ mm² (λ is calculated at lower resonating frequency of 3.56 GHz) with impedance bandwidths of 100 and 140 MHz and antenna gains of 1.91 and 3.04 dB at lower resonating frequency of 3.56 GHz and upper resonating frequency of 5.4 GHz, with omni-directional radiation pattern.

In literature, one does not encounter anchor shape antenna using the concept of gap coupling and parasitic patches. The design has been optimized for wireless local area network/worldwide interoperability for microwave access applications with a relatively low patch area (291.12 mm²) as compared to other reported antennas for wireless local area network/worldwide interoperability for microwave access applications. Transformed antenna and the actual experimental antenna behavior varies, but the resonant frequencies of the transformed antenna as observed by theoretical analysis and simulated results (by high frequency structure simulator) are reasonably close, and the percentage difference between the resonant frequencies (both at lower and upper bands) is within the permissible limit of 1-2.5 per cent. Results confirm the theoretical proposition of transformation of shapes in antenna design, which allows a designer to adapt the design shape according to the application.

The purpose of this paper is to study the high-frequency impacts of fast switching wide-bandgap transistors on electronic and motor designs. The high-frequency power converters, dedicated to driving high-speed motors, require specific models to design predictively electronic and motors.

From magnetic and electric models, the high-frequency parasitic elements for both electronics and motor are determined. Then, high-frequency circuit models accounting for of parasitic element extractions are built to study the wide bandgap transistors commutations and their impacts on motor windings.

The results of the models, for electronics and motors, are promising. The high-frequency commutation cell study is used to optimize the layouts and to improve the commutation behaviours and performances. The impact of the switching speed is highlighted on the winding voltage susceptibility. Then, the switching frequency and commutation rapidity can be both optimized to increase the performance of motor and electronics. The electronic model is validated by experimentations.

The method can be only applied to the existing motor and electronic designs. It is not taken into account in an automized global high-frequency optimizer.

Helped by magnetic and electric FEA calculations where the parasitic element extractions are performed. The switching frequency and commutation rapidity can be both optimized to increase the performance of motor and electronics.

This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method.

The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed.

The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage.

Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab.

The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.

This paper aims to present a method for the efficient reduction of networks modelling parasitic couplings in very‐large‐scale integration (VLSI) circuits.

The parasitic effects are modelled by large RLC networks and current sources for the digital switching currents. Based on the determined behaviour of the digital modules, an efficient description of these networks is proposed, which allows for a more efficient model reduction than standard methods.

The proposed method enables a fast and efficient simulation of the parasitic effects. Additionally, an extension of the reduction method to elements, which incorporate some supply voltage dependence to model the internal currents more precisely than independent current sources is presented.

The presented method can be applied to large electrical networks, used in the modelling of parasitic effects, for reducing their size. A reduced model is created which can be used in investigations with circuit simulators requiring a lowered computational effort.

Contrary to existing methods, the presented method includes the knowledge of the behaviour of the sources in the model to enhance the model reduction process.

The main aim of this study is the modelling of the interaction of on‐chip components with their electromagnetic environment.

The integrated circuit is decomposed in passive and active components interconnected by means of terminals and connectors which represent intentional and parasitic couplings of a capacitive and inductive nature. Reduced order models are extracted independently for each component.

The paper shows that one of the main theoretical problems encountered in the modelling of RF components is the difficulty to define a unique terminal voltage, independent of the integration path (this independence being a condition to allow the connection of the component in an electric circuit, where the voltage does not depend of the path shape). The concept of an electromagnetic circuit element that allows the interconnection between IC models is proposed as a solution for this drawback. The system is described either with EM field models, or by electric/magnetic circuits. By using the new concept of hooks, the EM interaction is described effectively with a reduced number of quantities.

Since hooks have a virtual character, their identification is the result of an optimization procedure. By increasing their number the model accuracy is improved as also is the computational effort. The optimal automatic identification of electric and magnetic hooks is the subject of further research. Currently, the hooks are placed manually.

The modelling of IC components with hooks is part of a new methodology that takes a layout description of typical RF functional blocks that will operate at RF frequencies up to 60 GHz and transform them into sufficiently accurate, reliable electrical simulation models, taking EM coupling and variability into account. This will decrease extra design iterations, over‐dimensioning or complete failures in the design cycle of RF‐IC.

For the first time, the concept of magnetic terminals is used to describe interactions in RF integrated circuits. These EM “hooks” are defined in mathematical terms, as proper boundary conditions. The concept of hooks is also new. The proposed modeling methodology for EM coupling is also new. The paper is useful for nEDA designers.

This paper describes the processing and electrical characterisation of an interconnection substrate technology called Combifilm. The study focuses on digital applications. According to calculations, the conductivity of the reference plane is shown not to be critical in the low gigahertz range. Electrical measurements were performed at low and high frequencies (up to 5 GHz). Measurements of the attenuation were compared with calculations. Crosstalk measurements were carried out from different line pitches and compared with numerical calculations. It was determined that a line pitch of 300 μm would give sufficiently low crosstalk for many digital applications. The SUSPENS model was used to estimate the performance of different substrate technologies for modules with high speed ECL circuits. Two hypothetical systems with different wiring demands were studied for each technology. For a module with low or moderate wiring demands, Combifilm yielded a silicon efficiency (silicon‐to‐substrate ratio) and a clock rate that were between the PCB‐based chip‐on‐board technology and thin‐film multilayer technology. The estimated clock rate was about 60% of that of the wire‐bonded thin‐film module. The module size of Combifilm was shown to be sensitive to the wiring demand, and for a high wiring density case the estimated size was approximately the same as for a chip‐on‐board module.

The purpose of this paper is to propose an analytical model for estimating propagation delay in coupled resistance-inductance-capacitance (RLC) interconnects.

With higher frequency of operation, longer length of interconnect and fast transition time of the signal, the resistor capacitor (RC) models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are required. In this paper, an analytical model for estimation of interconnect delay is developed for simultaneously switching lines. Two distributed RLC lines coupled inductively and capacitively are considered. To validate the proposed model, SPICE results are compared with the proposed analytical results. Each line in the coupled structure is terminated by a capacitive load of 30fF. The driving signal is considered symmetrical with equal rise and fall time of 5 ps and OFF/ON time of 45 ps. The model is validated for both in-phase and out of phase switching of lines.

It is observed that the model works well for both the phases of inputs switching. The derived expressions of delay exhibit complete physical insight, and the results obtained are in excellent agreement with SPICE results. Comparison of analytical delay with SPICE delay shows an average error of < 2.7 per cent.

The analytical expressions for interconnect delay are derived for the first time under simultaneously switching scenario. This model is useful to estimate delay across the inductively and capacitively coupled interconnects.

This paper aims to present the design of a compact quad-band coplanar-fed monopole antenna for tablet computer applications.

The antenna has the smallest size of 26 × 14 mm and supports GSM, Wi-Fi, WIMAX and Bluetooth. The proposed antenna consists of a coplanar fed main radiator, c-shaped stubs and parasitic meandered stub. The inverted c-shaped stubs enhance the bandwidth of upper frequencies. The resonance at 2.4 GHz is individually controlled by the coupled meandered stub.

The percentage bandwidth in the four operating bands are 8.7/4.12/27.8/13.3%. Furthermore, the antenna is integrated with the mock-up ground plane and specific absorption rate (SAR) calculations are performed. The estimated SAR is less than 1.6 W/kg for a 1 g body tissue. The gain and efficiency of the antenna are 3.56/4.37/4.97/6 dBi and 82.4/85/97.1/89.3%, respectively. The measured impedance and radiation characteristics of the fabricated prototype are in good correlation with the simulated results.

In the proposed work, vias and lumped elements are not used for lower band excitation, and most of the wireless applications in the tablet computers have been covered. Further, the effect of antenna with different orientation has been tested for the estimation of SAR.