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Recent advancements in the domain of smart communication systems and technologies have led to the augmented developments for very large scale integrated circuit designs in electro-magnetic applications. Increasing demands for low power, compact area and superior figure of merit–oriented circuit designs are the trends of the recent research studies. Hence, to accomplish such applications intended for optical communications, the transimpedance amplifier (TIA) was designed.

In this research work, the authors present a multi-layer active feedback structure which mainly composes a transimpedance stage and a gain stage followed by a low pass filter. This structure enables to achieve improved input impedance and superior gain. A simplified cascaded amplifier has also been designed in a hierarchical topology to improvise the noise effect further. The proposed TIA has been designed using Taiwan Semiconductor Manufacturing Company 45 nm complementary metal oxide semiconductor technology. Moreover, the thermal noise has been analyzed at −3 dB bandwidth to prove the reduction in thermal noise with increase in frequency for most of the devices used in the designed circuit.

The proposed differential TIA circuit was found to obtain the transimpedance gain of 50.1 dBO without applying any external bias current which is almost 8% improvised as compared to the conventional circuit. In addition to this, bandwidth achieved was 2.15 GHz along with only 38 W of power consumption, which is reasonably 100 times improvised in comparison of conventional circuit. Hence, the proposed differential TIA is suitable for the low power optical communications applications intended to work on low supply voltage.

The designed work is done by authors in university lab premises and is not copied from anywhere. To the best of the authors’ knowledge, it is 100% original.

This paper aims to achieve two main objectives. First, to introduce to the literature a new versatile active building block, namely, voltage differencing differential voltage current conveyor (VD-DVCC) for analog signal processing applications. Second, to design a novel electronically tunable mixed-mode universal filter. The designed filter provides low-pass, high-pass, band-pass, band-reject and all-pass responses in voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM) and trans-admittance-mode (TAM).

The proposed filter uses two VD-DVCCs, three resistors and two capacitors. All the capacitors used are grounded, which is advantageous from the monolithic integration point of view. The VD-DVCC is designed and validated in Cadence software using CMOS 0.18 µm process design kit from Silterra Malaysia at a supply voltage of ±1 V.

The proposed novel filter enjoys many attractive features including as follows: the ability to operate in all four modes, no requirement of capacitive matching, tunability of quality factor (Q) independent of pole frequency, availability of both inverting and non-inverting outputs for VM and TIM mode, high output impedance explicit current output for CM and TAM, no requirement for double/negative input signals (voltage/current) for response realization and low active and passive sensitivities. The filter is designed for a pole frequency of 5.305 MHz. The obtained results bear a close resemblance with the theoretical findings.

The proposed novel filter structure requires a minimum number of active and passive components and provides operation in all four operating modes. The filter will find application in structures of mixed-mode systems.