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The purpose of this paper is to propose a DC-port voltage balance strategy realizing it by logic combination modulation (LCM). This voltage balance strategy is brief and high efficient, which can be used in many power electronic devices adopting the cascaded H-bridge rectifier (CHBR) such as power electronic transformer (PET).

The CHBR is typically as a core component in the power electronic devices to implement the voltage or current conversion. The modulation method presented here is aiming to solve the voltage imbalance problem occurred in the CHBR with more stable work station and higher reliability in ordinary operating conditions. In particular, by changing the switch states smoothly and quickly, the DC-port voltage can be controlled as the ideal value even one of the modules in CHBR is facing the load-removed problem.

By using the voltage balance strategy of LCM, the problem of voltage imbalance occurring in three-phase cascaded rectifiers has been solved properly. With the lower modulation depth, the efficiency of the strategy is shown to be better and stronger. The strategy can work reliably and quickly no matter facing the problem as load-removed change or the ordinary operating conditions.

The limitation of the proposed DC-port voltage balance strategy is calculated and proved, in a three-module CHBR, the LCM could balance the DC-port voltage while one module facing the load-removed situation under 0.83 modulation depth.

This paper provides a useful and particular voltage balance strategy which can be used in the topology of three-phase cascaded rectifier. The value of the strategy is that a brief and reliable voltage balance method in the power electronic devices can be achieved. What is more, facing the problem, such as load-removed, in outport, the strategy can response quickly with no switch jump and switch frequency rising.

The purpose of this paper is to design a cascaded Multilevel inverter with reduce number of switches for high power applications. This paper came up with an innovative three-phase multilevel inverter (MLI) topology, which is a cascaded structure based on classical three-legged voltage source inverter (VSI) bridges as an individual module. The prominent advantage of this topology is that it requires only one direct current (DC) link system. The main characteristic of it is that a higher number of voltage levels can be achieved with considerably a smaller number of semiconductor switches, which improves the reliability, power quality, cost and size of the system significantly.

The individual modules are cascaded through three-phase transformers to provide higher voltage at the output with the higher number of voltage levels. In this work, the phase-shifted pulse width modulation technique is implemented to verify the result.

The proposed topology is compared with three-phase cascaded H-bridge MLI (CHB-MLI) and a modified CHB-MLI topology and found better in many aspects. The proposed MLI can produce a higher number of voltage levels with fewer semiconductor switches and associated triggering circuitry. As the device count in the proposed MLI is less compared to other MLI discussed, it tends to have less switching and conduction loss which increases the efficiency and reliability. As the number of level increases, the voltage profile and the total harmonic distortion of the proposed MLI improves.

This is a transformer-based modular cascaded MLI, which is based on classical VSI bridges. Here in this topology, a single module provides all three phases. So, a single string of cascaded modules is enough for three-phase multilevel voltage generation.

Multilevel inverter (MLI) is an established design approach for inverter applications in medium-voltage and high-voltage range of applications. An asymmetric design synthesizes multiple DC input voltage sources of unequal magnitudes to generate a high-quality staircase sinewave comprising a large number of steps or levels. However, the implications of using sources of unequal magnitudes results in the requirements of a large variety of inverter switches and higher magnitudes of the total blocking voltage (TBV) rating of the inverter, which increase the cost. The purpose of this study is to present a solution based on algorithms for establishing DC source magnitudes and other design parameters.

The approach used in this study is to develop algorithms that bring an asymmetric cascaded MLI (ACMLI) design close to symmetric design. This approach then reduces the variety of switch ratings and minimizes the TBV of the inverter. Thus, the benefits of both asymmetric design (generation of a large number of voltage levels in the output waveform) and symmetric design (modularity) are achieved. The proposed algorithms can be applied to a number of ACMLI topologies, including classical cascaded H-bridge (CHB). The effectiveness of the proposed algorithms is validated by simulation in Matlab-Simulink and experimental setup.

Two new algorithms are proposed that reduce the number of variety of switches to just three. The variety can further be reduced to two under a specified condition. The algorithms are compared with the existing ones, and the results are promising in minimizing the TBV rating of the inverter, which results in cost reduction as well. For a specific case of four CHBs, the proposed Algorithm-1 produced 27% and Algorithm-2 produced 53% higher levels. Moreover, the presented algorithms produced minimum values of the TBV and resulted in minimum cost of inverter.

The proposed algorithms are novel in structure and have achieved the targeted values of minimized switch variety and reduced TBV ratings. Due to less variety, the inverter achieves a near symmetric design, which enables to attain the added advantages of modularity and reduced difference of power sharing among the DC sources.

The purpose of this paper is to implement a finite set model predictive control algorithm to a shunt (or parallel), multilevel (cascaded H-bridge) active power filter (APF). Specifically, the purpose is to get a controller that could compensate the mains current and, at the same time, to control the voltages of its capacitors. This strategy avoids the use of multiple PWM carriers or another type of special modulator, and requires a relatively low processing power.

This paper is focussed in the application of the predictive controller to a single-phase parallel APF composed for two H-bridges connected in series. The same methodology can be applied to a three-phase APF. In the DC buses of each H-bridge, a floating capacitor was connected, whose voltage is regulated by the predictive controller. The controller is composed by, first, a model for the charge/discharge dynamics for each floating capacitor and a model for the output current of the APF; second, a cost function; and third, an optimization algorithm that is able to control all these variables at the same time, choosing in each sample period the best combination of firing pulses.

The controller can track the voltage references, compensate the current harmonics and compensate reactive power with an algorithm that evaluates only the three nearest voltage levels to the last voltage level applied in the inverter. This strategy decreases the number of calculations required by the predictive algorithm. This controller can be applied to the general case of a single-phase multilevel APF of N-levels and extend it to the three-phase case without major problems.

The implemented controller, when the authors consider a constant sample time, gives a mains current with a Total Harmonic Distortion (THD-I) slightly greater in comparison with the base algorithm (that evaluates all the voltage levels). However, when the authors consider the processing times under the same processor, the implemented algorithm requires less time to get the optimal values, can get lower sampling times and then a best performance in terms of THD-I. To implement the controller in a three-phase APF, a faster Digital Signal Processor would be required.

The implemented solution uses a model for the charge/discharge of the capacitors and for the filter current that enable to operate the cascaded multilevel inverter with asymmetrical voltages while compensates the mains currents, with a predictive algorithm that requires a relatively low amount of calculations.

These implementations not only generate excessive voltage levels to enhance the quality of power but also include a detailed investigating of the various modulation methods and control schemes for multilevel inverter (MLI) topologies. Reduced harmonic modulation technology is used to produce 11-level output voltage with the production of renewable energy applications. The simulation is done in the MATLAB/Simulink for 11-level symmetric MLI and is correlated with the conventional inverter design.

This paper is focused on investigating the different types of asymmetric, symmetric and hybrid topologies and control methods used for the modular multilevel inverter (MMI) operation. Classical MLI configurations are affected by performance issues such as poor power quality, uneconomic structure and low efficiency.

The variations in both carrier and reference signals and their performance are analyzed for the proposed inverter topologies. The simulation result compares unipolar and bipolar pulse-width modulation (PWM) techniques with total harmonic distortion (THD) results. The solar-fed 11-level MMI is controlled using various modulation strategies, which are connected to marine emergency lighting loads. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by using SPARTAN 3A field programmable gate array (FPGA) board and the least harmonics are obtained by improving the power quality.

The simulation result compares unipolar and bipolar PWM techniques with THD results. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by a SPARTAN 3A field programmable gate array (FPGA) board, and the power quality is improved to achieve the lowest harmonics possible.

The purpose of this paper is to propose a new converter topology for integrating PV plants constituted by many panels into the grid. The converter is capable of implementing MPPT algorithms on different subset of modules and can balance the different energy supplied by panels differently irradiated. The output voltage presents a very low ripple also if small filters are used for grid connection.

In the paper, at first the converter configuration is presented. Then a control strategy for obtaining, at the same time the distributed MPPT and the power balancing on the three phases is proposed. Finally, by means of numerical simulations, the good performances of the proposed converter are shown.

The proposed converter, lent from MMC configurations, is deeply studied and a suitable control strategy is well analyzed in the paper. Analytical model for voltage and current balancing are given.

The analysis presented in the paper complete some studies started in the last years and partially presented in previous scientific papers. It reaches a final point and gives all the specific for the realization of the converter and of its control.

The paper gives all the instrument to design and realize a PV power plant integrated into building façade.

The converter and the control for voltage and current balancing presented in this paper represent a significant original contribution of this work.

Multilevel inverters play a major role in the development of high-power industrial applications. In traditional low-level inverters (e.g. 2-level), the switching frequency is restricted and the harmonic spectrum of the system is hard to meet power requirements. Similarly, high-level inverters consist of a large number of switches, complex modulation techniques and complex hardware architecture, which results in high power loss and a significant amount of harmonic distortion. Furthermore, it is a must to ensure that every switch experiences the same stress of voltage and current. The purpose of this paper is to present an inverter topology with lower conduction and switching losses via reduced number of switches and equal voltage source-sharing technique.

Herein, the authors present a cascaded multilevel inverter having less power switches, a simple modulation technique and an equal voltage source-sharing phenomenon implementation.

The modulation technique becomes more complex when equal voltage source-sharing is to be implemented. In this study, a novel topology for the multilevel inverter with fewer switches, novel modulation technique, equal voltage source-sharing and Inductor-Capacitor-Inductor filter implementation is demonstrated to the reduce harmonic spectrum and power losses of the proposed system.

The nine-level inverter design is validated using software simulations and hardware prototype testing; the power losses of the proposed inverter design are elaborated and compared with the traditional approach.

The purpose of this paper is to introduce a new concept in selecting the values of the DC source voltages in cascaded multi‐level inverters in order to improve the output voltage THD.

In cascaded multi‐level inverters, it is usually assumed that the DC sources have the same constant voltage and output harmonics minimization is accomplished by applying proper switching angles. Employing different DC voltages with proper ratios can result in further reduction of the harmonics. After formulation of the system, i.e. describing the inverter's output voltage components in terms of the switching angles and unequal DC source voltages, a rule is applied to obtain the step heights of the staircase output waveform (DC source voltages), so that the output waveform becomes as close to the required fundamental sine wave as possible. Substituting the obtained DC source voltages into the harmonics elimination equations results in a set of equations, which are functions of switching angles only. Solving these equations leads to proper switching angles, which, regardless of the fundamental component's value, provide the specified harmonic conditions. The output voltage is then controlled by DC sources voltage regulation.

Computer simulations show that employing the proposed concept results in substantial improvement in the harmonic minimization, as well as, extending the operating range of the inverter, compared to the conventional methods with equal DC source voltage multi‐level inverters.

The proposed concept according to which the ratio of the DC source voltages are determined, is original.

The active power filter with two-level inverter needs a high-rating coupling transformer for high-power applications. This complicates the control and system becomes bulky and expensive. The purpose of this paper is to motivate the use of multilevel inverter as harmonic filter, which eliminates the coupling transformer and allows direct control of the power circuit. The advancement in artificial intelligence (AI) for computation is explored for controller design.

The proposed scheme has a five-level cascaded H-bridge multilevel inverter (CHBMLI) as a harmonic filter. The control scheme includes one neural network controller and two fuzzy logic-based controllers for harmonic extraction, dc capacitor voltage balancing, and compensating current adjustment, respectively. The topology is modeled in MATLAB/SIMULINK and implemented using dSPACE DS1103 interface for experimentation.

The exhaustive simulation and experimental results demonstrate the robustness and effectiveness of the proposed topology and controllers for harmonic minimization for RL/RC load and change in load. The comparison between traditional PI controller and proposed AI-based controller is presented. It indicates that the AI-based controller is fast, dynamic, and adaptive to accommodate the changes in load. The total harmonic distortion obtained by applying AI-based controllers are well within the IEEE519 std. limits.

The simulation of high-power, medium-voltage system is presented and a downscaled prototype is designed and developed for implementation. The laboratory module of CHBMLI-based harmonic filter and AI-based controllers modeled in SIMULINK is executed using dSPACE DS1103 interface through real time workshop.

Maintaining a balanced neutral point, reducing power loss, execution time are important criteria for the controlling of neutral point clamped (NPC) inverter. However, it is tough to meet all the challenges and also supplying the load current within the harmonic limit. This paper aims to maintain load current quality within the Institute of Electrical and Electronics Engineers 519 standard and meet the above-mentioned challenges.

The output load current of a three-level simplified neutral point clamped (3 L-SNPC) inverter is controlled in this paper using model predictive control (MPC). The 3 L-SNPC inverters is considered because fewer semiconductor devices are used in this topology; this will enhance the reliability of the system. MPC is used as a controller because it can handle the direct current-link capacitors’ voltage balancing problem in a very intuitive way. The proposed 3 L-SNPC yields similar current total harmonic distortion (THD), transient and steady-state responses, voltage stress and over current protection capability as the conventional NPC inverter. To reduce the computational burden of the proposed SNPC system, two simplified MPC strategies are proposed, namely, single voltage vector prediction-based MPC and selective voltage vector prediction-based MPC.

The system shows a current THD of 2.33% at 8.96 kHz. The overall loss of the system is reduced significantly to be useful in medium power applications. The required execution times for the simplified MPC strategies are tested on the hardware dSPACE 1104 platform. It is found that the single voltage vector prediction-based MPC and the selective voltage vector prediction-based MPC are computationally efficient by 8.28% and 62.9%, respectively, in comparison with the conventional MPC-based conventional NPC system.

Multiple system constraints are considered throughout the paper and also compare the SNPC to the conventional NPC inverter. Proper current tracking, over-current protection, overall power loss reduction especially switching loss and maintaining capacitor voltages balance at a neutral point are achieved. The improvement of execution time has also been verified and calculated using hardware-in-loop of the dSPACE DS1104 platform.