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The purpose of this paper is to optimize assembly processes in order to minimize defects in the assembly of 01005 chip components.

During the study, solder paste printing process‐related variables, such as solder paste type, stencil type, and stencil opening ratio, and pick and place process‐related methods, such as vision camera type and vacuum pickup nozzle type were evaluated with the goal of achieving a high‐yield assembly solution for 01005 chip components. A test board was used in a series of designed experiments to optimize the solder paste printing, pick and placement, and reflow processes. Assembly defects were analyzed as a function of the stencil design and the assembly processes.

The results of the study indicated that both electroformed and electropolished laser‐cut stencils had a comparable print quality with respect to the solder volume delivered to the pads. In terms of assembly yield performance, type 4 (size range: 20‐38 μm) solder paste with a smaller sphere size gave a better overall yield and better paste deposition on the pad, if used on a 0.08‐mm thick electroformed stencil with a 90 per cent aperture. Temperature cycling between −65 and 150°C, with up to 1,500 cycles, showed that no cracks were observed at the solder joints due to temperature cycling. The process and design change required for achieving a robust manufacturing process have been indicated and reported.

The results of this work provide process recommendations for the implementation of 01005‐sized chip components assembly in mass production processes.

This paper aims to study the influence of reflow atmosphere and placement accuracy on the solderability of 01005 capacitor/SAC305 solder joints.

The 01005 capacitors were mounted on OSP-coated pads, and the samples were fabricated in four different atmospheres, i.e. 200 ppm O₂/N₂, 1,000 ppm O₂/N₂, 3,000 ppm O₂/N₂ and air. After the reflow process, visual inspection and X-ray detection were carried out to examine the solder joint shapes and possible defects. Some of the samples fabricated in different conditions were cross-sectioned and the solder joint microstructures were analyzed. On the other hand, besides placing the components on their normal pad positions, a 50 per cent offset of the x-axis (long axis) or y-axis (short axis) was introduced into the chip mounter programs to evaluate the 01005 capacitor’s assembly sensitivity to placement accuracy. The process-induced defects were investigated.

Experimental results indicated that an N₂-based protective atmosphere was necessary for 01005 type assembly, as it could obviously improve the 01005 solder joint quality, compared with the air condition. The protective atmosphere had little effect on the appearance, quality and microstructure of solder joints when the oxygen concentration was below 3,000 ppm. But a very low oxygen concentration could increase the risk of tombstoning defects for the assembly process. The N₂-based protective atmosphere containing 1,000-2000 ppm O₂ was acceptable and appropriate for the assembly of tiny components.

The results of this work provide a set of reflow process parameters and recommendations for 01005 size component assembly in manufacturing.

The purpose of this paper is to study the effect of the electropolishing time of stencil manufacturing parameters and solder‐mask definition methods of PCB pad design parameters on the performance of solder paste stencil printing process for the assembly of 01005 chip components.

During the study, two types of stencils were manufactured for the evaluations: electroformed stencils and electropolished laser‐cut stencils. The electroformed stencils were manufactured using the standard electroforming process and their use in the paste printing process was compared against the use of an electropolished laser‐cut stencil. The electropolishing performance of the laser‐cut stencil was evaluated twice at the following intervals: 100 s and 200 s. The performance of the laser‐cut stencil was also evaluated without electropolishing. An optimized process was established after the polished stencil apertures of the laser‐cut stencil were inspected. The performance evaluations were made by visually inspecting the quality of the post‐surface finishing for the aperture wall and the quality of that post‐surface finishing was further checked using a scanning electron microscope. A test board was used in a series of designed experiments to evaluate the solder paste printing process.

The results demonstrated that the length of the electropolishing time had a significant effect on the small stencil's aperture quality and the solder paste's stencil printing performance. In this study, the most effective electropolishing time was 100 s for a stencil thickness of 0.08 mm. The deposited solder paste thickness was significantly better for the enhanced laser‐cut stencil with electropolishing compared to the conventional electroformed stencils. In this printing‐focused work, print paste thickness measurements were also found to vary across different solder‐mask definition methods of printed circuit board pad designs with no change in the size of the stencil aperture. The highest paste value transfer consistently occurred with solder‐mask‐defined pads, when an electropolished laser‐cut stencil was used.

Due to important improvements in the quality of the electropolished laser‐cut stencil, and based on the results of this experiment, the electropolished laser‐cut stencil is strongly recommended for the solder paste printing of fine‐pitch and miniature components, especially in comparison to the typical laser‐cut stencil. The advantages of implementing a 01005 chip component mass production assembly process include excellent solder paste release, increased solder volume, good manufacture‐ability, fast turnaround time, and greater cost saving opportunities.

This study aims to focus on the passive components of System in Package SiP modules and discusses the geometric pad designs for 01005-sized passive components, the front end design of the hole size and shape of the stencil and the parameters of the stencil sidewall coating, to determine the optimum parameter combination.

This study plans and conducts experiments, where a L8(27) inner orthogonal array is built to consider the control factors, including a L4(23) outer orthogonal array to consider the noise factor, and the experimental data are analyzed by using the technique for order preference by similarity to ideal solution multi-quality analysis method.

The results show that the optimum design parameter level combination is that the solder mask opening pad has no solder mask in the lower part of the component, the pad width is 1.1 times that of the component width, the pad length is 1.75 times that of the electrode tip length, the pad spacing is 5 mil, the stencil open area is 90% of the pad area, the stencil opening corner has a 3 mil chamfer angle, and the stencil sidewall is free of nano-coating.

The parameter design and multi-quality analysis method, as proposed in this study, can effectively develop the layout of passive components on a high-density SiP module substrate, to stabilize the process and increase the production yield.

The ever present need for the miniaturization of electronic assemblies has driven the size of passive components to as small as the 01005 package size. However, the packaging standards for these components are still under development. The purpose of this work is to report results from experiments designed to establish optimum process parameters, pad sizes and component clearances for the surface mounting of 01005 passive components.

The experiments were designed using MODDE, an experimental design software tool, and were carried out with both 01005 capacitors and resistors. All the assembled components were examined under microscope and judged according to industrial workmanship standards.

It was found that a viable solder paste printing process for the assembly of 01005 components can be achieved with a 75 μm thick stencil. Type 5 solder paste achieved a similar printing performance to type 4. Under the experimental conditions used, the optimum pad dimensions for the 01005 capacitors were 210 μm length, 220 μm width, 160 μm separation and for the resistors were 190 μm length, 220 μm width, 160 μm separation. The smallest component clearance to reliably avoid bridging was found to be 100 μm. A high placement force of 3.5 N was found to cause cracking of 01005 resistors.

From this work, a surface mount process for 01005 passive components is established and it is concluded that electronics packaging density can be increased through the assembly of these small components. In the near future, the widespread use of them will definitely facilitate a further reduction in the size of electronic assemblies, especially in handheld and portable devices.

To propose a solution procedure to minimize/eliminate tombstoning defects in small chip components with different micro via‐in pad designs for high density module assembly.

Four different micro via‐in pad designs were compared (via‐hole diameter): ultra small via‐in pads (10 μm), small via‐in pads (20 μm) and large via‐in pads (60 μm), as well as designs with no via‐in pads and capped via‐in pads. Two process variables were also evaluated for the goal of achieving a high‐yield assembly solution in micro via‐in pad and lead‐free solder conditions. Potential factors such as the preheat conditions of the reflow profile and stencil aperture size, which might affect tombstoning in components with micro via‐in pads, were investigated.

The results indicated that the micro via‐in pad design significantly increased the tombstoning; thus, tombstoning did not occur in components with both no via‐in pads and capped via‐in pads. Capped via‐in pads exhibited the best results in preventing tombstoning and provided a wide process window for the selection of process parameters. The results showed that tombstoning was found to decrease with both increasing stencil opening ratio and use of reflow profile with long‐preheat condition.

The paper's findings provide certain process guidelines for high density module assemblies with via‐in pad design. The strategy is to prevent tombstoning by adopting capped via‐in pad design if possible when employing micro via‐in pad technology.

To optimize the printed circuit board design and assembly processes to minimize defects in the assembly of 01005 size chip resistors.

A test board was designed with a range of pad sizes, pad shapes, pad spacings and pad orientations. This test board was used in a series of designed experiments to optimize the printing, placement and reflow processes. Assembly defects were analyzed as a function of board design and assembly processes.

An electroformed, 76 μm stencil yielded a robust paste printing process and higher process capability indices (C_p) compared to a 102 μm stencil. Nitrogen reflow was required to achieve good solder wetting due to the high surface‐to‐volume ratio of the solder deposits. With regard to bridging defects, no defects were observed if the pad‐to‐pad spacing for parallel resistors was 150 μm or larger. Rectangular pads with no vias‐in‐pad and designed at 90 percent of nominal pad size (pad size type 2) with the ramp profile, independent of 0° or 90° resistor orientation yielded the lowest number of defects. Given the undersized pads on the actual board, the 90 percent pad average width was 170 μm (versus a design value of 183 μm) and the measured width of the 01005 chip resistor was 180 μm. Thermal cycle reliability testing of the solder joints with this pad size showed no failures after 1,000 thermal cycles.

The results of this work provide a set of design and assembly processes recommendations for those who must implement 01005 size component assembly in production.