Evaluation of Cu/SnAg microbump bonding processes for 3D integration using wafer‐level underfill film

Abstract

Purpose

3D chip stacking is a key technology for 3D integration in which two or more chips are stacked with vertical interconnections. In the case of multi chip stacking with fine pitch microbump connections, capillary dispensing presents big limitations in terms of cost and processability. The purpose of this paper is to describe the way in which wafer‐level underfill (WLUF) process development was carried out with particular emphasis on microbump height coplanarity, bonding pressure distribution and the alignment of the microbumps. A three factorial design of experiment (DOE) was also conducted to enhance the understanding of the factors impacting the WLUF process such as bonding pressure, temperature and time on reliability test.

Design/methodology/approach

B‐staged WLUF was laminated on an 8″ wafer with a 30 μm pitch bump structure of 8 μm Cu/5 μm Sn2.5Ag Pb‐free solder. After wafer dicing, the chip with the WLUF was assembled on a substrate chip with the same bump structure using a high accuracy bonder. The substrate chip had metalisation (wiring) to enable evaluation of the electrical characteristics of the bonded daisy chain chips as they varied with material bonding process conditions and reliability testing.

Findings

The WLUF bonding process development pertaining to the processability and reliability for the flip chip assembly using Cu/SnAg microbumps was successful in this work.

Originality/value

The development of a WLUF bonding process that offers reliability for flip chip assembly using Cu/SnAg microbumps has been presented in this work. The critical steps, such as alignment of the WLUF coated chip with the substrate chip and void elimination, which enable this technology to work were optimised.

Citation

Yang, T., Kao, K., Cheng, R., Chang, J. and Zhan, C. (2012), "Evaluation of Cu/SnAg microbump bonding processes for 3D integration using wafer‐level underfill film", Soldering & Surface Mount Technology, Vol. 24 No. 4, pp. 287-293. https://doi.org/10.1108/09540911211262575