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Article
Publication date: 4 October 2021

Zhen Pan and Fenglian Sun

The purpose of this paper is to design a novel die-attach composite joint for high-temperature die-attach applications based on transient liquid phase bonding. Moreover, the…

Abstract

Purpose

The purpose of this paper is to design a novel die-attach composite joint for high-temperature die-attach applications based on transient liquid phase bonding. Moreover, the microstructure, shear strength, electrical property, thermal conductivity and aging property of the composite joint were investigated.

Design/methodology/approach

The composite joint was made of microporous copper and Cu3Sn. Microporous copper was immersed into liquid Sn to achieve Sn-microporous copper composite structure for die attachment. By the thermo-compression bonding, the Cu3Sn-microporous copper composite joint with a thickness of 100 µm was successfully obtained after bonding at 350 °C for 5 min under a low pressure of 0.6 MPa.

Findings

After thermo-compression bonding, the resulting interconnection could withstand a high temperature of at most 676 °C, with the entire Sn transforming into Cu3Sn with high remelting temperatures. A large shear strength could be achieved with the Cu3Sn-microporous copper in the interconnections. The formed bondlines demonstrated a good electrical and thermal conductivity owing to the large existing amount of copper in the interconnections. Furthermore, the interconnection also exhibited excellent reliability under high temperature aging at 300 °C.

Originality/value

This die-attach composite joint was suitable for power devices operating under high temperatures or other harsh environments.

Details

Soldering & Surface Mount Technology, vol. 34 no. 3
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 1 February 1994

J. Eldring, E. Zakel and H. Reichl

Ball‐bumping is a flexible low cost bumping technology based on the conventional wire bonding procedure. It is applicable to single chips or whole wafers as well as to substrates…

Abstract

Ball‐bumping is a flexible low cost bumping technology based on the conventional wire bonding procedure. It is applicable to single chips or whole wafers as well as to substrates. As established wire‐bonding machines can be used, expensive bumping‐process equipment for phototooling and plating is not necessary. Flip‐chip bonding is the most advantageous attach method of high frequency applications. Compared with wire‐bonding and TAB it allows the highest contact density, the shortest signal paths and lowest interconnection parasitics. The reduced pad sizes and pitches, not only of GaAs devices, demand a well controlled bump deformation during flip‐chip bonding. This work develops process parameters for the flip‐chip bonding of silicon and GaAs devices with respect to the best interconnection result by lowest bonding force and ball‐bump deformation. Ball‐bumps with diameters of 50 and 80 urn (2.0 and 3.2 mils) were created using 98% AuPd bump wire with diameters of 18 µm (0.7 mil) and 25 µm (1.0 mil) respectively. Ball‐bumping with a minimal pitch of 70 µm (2.8 mils) has been achieved. A special preparation allowed the shear test investigation of each bump/pad interface after flip‐chip attach. Bonding forces of 20 and 25 cN/bump respectively lead to a good welding in the bump/substrate interface due to the special shape of ball‐bumps. For silicon devices which have a pad metallisation of aluminium, the shear forces of the bump/pad interface increase after flip‐chip bonding, too. No cratering of GaAs and silicon occurs after flip‐chip bonding due to a low bonding force ramp of 5 cN/s and 10 cN/s respectively. The flip‐chip attach of a Fujitsu FLR 016 GaAs‐FET which has pad sizes of 35 urn is demonstrated. In this case, substrate bumping is the more advantageous bumping method. The feasibility of fine‐pitch TAB attach using ball‐bumps is introduced. 100 µm (3.9 mils) pitch silicon devices with 328 pads were ball‐bumped for both solder and thermalcompression TAB. Bond forces were in the range of 9–11 cN/bump and 15–21 cN/bump respectively. Pull forces of approximately 30 cN/lead show good results of the bump/lead interconnection after TAB.

Details

Microelectronics International, vol. 11 no. 2
Type: Research Article
ISSN: 1356-5362

Article
Publication date: 27 December 2022

Ge Li, Qiushi Kang, Fanfan Niu and Chenxi Wang

Bumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s…

Abstract

Purpose

Bumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry’s continuous development, which achieves the stacks of chips vertically connected via through-silicon via. Surface-activated bonding (SAB) and thermal-compression bonding (TCB) are used, but both have some shortcomings. The SAB method is overdemanding in the bonding environment, and the TCB method requires a high temperature to remove copper oxide from surfaces, which increases the thermal budget and grossly damages the fine-pitch device.

Design/methodology/approach

In this review, methods to prevent and remove copper oxidation in the whole bonding process for a lower bonding temperature, such as wet treatment, plasma surface activation, nanotwinned copper and the metal passivation layer, are investigated.

Findings

The cooperative bonding method combining wet treatment and plasma activation shows outstanding technological superiority without the high cost and additional necessity of copper passivation in manufacture. Cu/SiO2 hybrid bonding has great potential to effectively enhance the integration density in future 3D packaging for artificial intelligence, the internet of things and other high-density chips.

Originality/value

To achieve heterogeneous bonding at a lower temperature, the SAB method, chemical treatment and the plasma-assisted bonding method (based on TCB) are used, and surface-enhanced measurements such as nanotwinned copper and the metal passivation layer are also applied to prevent surface copper oxide.

Details

Microelectronics International, vol. 40 no. 2
Type: Research Article
ISSN: 1356-5362

Keywords

Article
Publication date: 14 May 2021

F Sun, Zhen Pan, Yang Liu, Xiang Li, Haoyu Liu and Wenpeng Li

The purpose of this paper is to quickly manufacture full Cu3Sn-microporous copper composite joints for high-temperature power electronics applications and study the microstructure…

Abstract

Purpose

The purpose of this paper is to quickly manufacture full Cu3Sn-microporous copper composite joints for high-temperature power electronics applications and study the microstructure evolution and the shear strength of Cu3Sn at different bonding times.

Design/methodology/approach

In this paper, a novel structure of Cu/composite solder sheet/Cu was designed. The composite solder sheet was made of microporous copper filled with Sn. The composite joint was bonded by thermo-compression bonding under pressure of 0.6 MPa at 300°C. The microstructure evolution and the growth behavior of Cu3Sn at different bonding times were observed by electron microscope and metallographic microscope. The shear strength of the joint was measured by shear machine.

Findings

At initial bonding stage the copper atoms in the substrate and the copper atoms in the microporous copper dissolved into the liquid Sn. Then the scallop-liked Cu6Sn5 phases formed at the interface of liquid Sn/microporous copper and liquid Sn/Cu substrates. During the liquid Sn changing to Cu6Sn5 phases, Cu3Sn phases formed and grew at the interface of Cu6Sn5/Cu substrates and Cu6Sn5/microporous copper. After that the Cu3Sn phases continued to grow and the Cu3Sn-microporous copper composite joint with a thickness of 100 µm was successfully obtained. The growth rule of Cu3Sn was parabolic growth. The shear strength of the composite joints was about 155 MPa.

Originality/value

This paper presents a novel full Cu3Sn-microporous copper composite joint with high shear strength for high-temperature applications based on transient liquid phase bonding. The microstructure evolution and the growth behavior of Cu3Sn in the composite joints were studied. The shear strength and the fracture mechanism of the composite joints were studied.

Details

Soldering & Surface Mount Technology, vol. 33 no. 5
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 14 September 2012

Tsung‐Fu Yang, Kuo‐Shu Kao, Ren‐Chin Cheng, Jing‐Yao Chang and Chau‐Jie Zhan

3D chip stacking is a key technology for 3D integration in which two or more chips are stacked with vertical interconnections. In the case of multi chip stacking with fine pitch…

Abstract

Purpose

3D chip stacking is a key technology for 3D integration in which two or more chips are stacked with vertical interconnections. In the case of multi chip stacking with fine pitch microbump connections, capillary dispensing presents big limitations in terms of cost and processability. The purpose of this paper is to describe the way in which wafer‐level underfill (WLUF) process development was carried out with particular emphasis on microbump height coplanarity, bonding pressure distribution and the alignment of the microbumps. A three factorial design of experiment (DOE) was also conducted to enhance the understanding of the factors impacting the WLUF process such as bonding pressure, temperature and time on reliability test.

Design/methodology/approach

B‐staged WLUF was laminated on an 8″ wafer with a 30 μm pitch bump structure of 8 μm Cu/5 μm Sn2.5Ag Pb‐free solder. After wafer dicing, the chip with the WLUF was assembled on a substrate chip with the same bump structure using a high accuracy bonder. The substrate chip had metalisation (wiring) to enable evaluation of the electrical characteristics of the bonded daisy chain chips as they varied with material bonding process conditions and reliability testing.

Findings

The WLUF bonding process development pertaining to the processability and reliability for the flip chip assembly using Cu/SnAg microbumps was successful in this work.

Originality/value

The development of a WLUF bonding process that offers reliability for flip chip assembly using Cu/SnAg microbumps has been presented in this work. The critical steps, such as alignment of the WLUF coated chip with the substrate chip and void elimination, which enable this technology to work were optimised.

Details

Soldering & Surface Mount Technology, vol. 24 no. 4
Type: Research Article
ISSN: 0954-0911

Keywords

Article
Publication date: 1 December 1996

R.D. Schueller and A.P. Plepys

Tape ball grid array (TBGA) packages offer many of theadvantages of plastic BGAs, namely excellent durability, improved board space utilisation and ease ofsurface mount assembly…

241

Abstract

Tape ball grid array (TBGA) packages offer many of the advantages of plastic BGAs, namely excellent durability, improved board space utilisation and ease of surface mount assembly along with the associated yield improvements. TBGA packages go a step further, however, and offer the added benefits of improved signal integrity, better heat dissipation, and extendability to higher pin counts. This paper outlines the design and material selection process to produce a low‐cost TBGA which allows the wire bonding of a die. This type of package offers an attractive solution for applications requiring mid to high I/O capability and good electrical and thermal properties. Preliminary results have demonstrated the feasibility of wire bonding to this package at temperatures up to 200°C.

Details

Circuit World, vol. 22 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 21 September 2010

Bo Tao, Zhouping Yin and Youlun Xiong

From the viewpoint of degree of cure, the purpose of this paper is to find how to improve the reliability of flip‐chip packaging modules based on an anisotropically conductive…

Abstract

Purpose

From the viewpoint of degree of cure, the purpose of this paper is to find how to improve the reliability of flip‐chip packaging modules based on an anisotropically conductive adhesive film (ACF) interconnection process.

Design/methodology/approach

The work begins by revealing the correlation of adhesive strength and contact resistance of flip‐chip joint interfaces with the degree of cure of the ACF. The effect of different degrees of curing on the electrical and mechanical properties of some typical ACF‐interconnected joints is studied, and the optimum degree of cure is suggested to achieve highly reliable ACF joints, where the performance variations of the adhesion strength and contact resistance are considered simultaneously. First, the degradation data of the contact resistance of some ACF assemblies, bonded with several degrees of cure, is collected during a standard high‐hydrothermal fatigue test. The resistance distribution is verified using a two‐parameter Weibull model and the distribution parameters are estimated, respectively. After that, a reliability analysis method based on the degradation data of contact resistance is achieved, instead of the traditional failure time analysis, and the reliability index, as well as the mean‐time‐to‐degradation of the ACF joints, as a function of the degree of cure, is deduced, through which the optimum degree of cure value and recommend range are suggested.

Findings

Numerical analysis and calculations are performed based on the experiments. Results show that the optimum degree of cure to achieve highly reliable joints is 83 per cent, and the recommend range is from 82 to 85 per cent for the ACF tested (considering a 95 per cent confidence interval).

Originality/value

The paper provides important support for optimizing the curing process for various ACF‐based packaging applications, such as chip‐on‐glass packaging of liquid crystal displays and flip‐chip bonding of radio frequency identification, etc.

Details

Soldering & Surface Mount Technology, vol. 22 no. 4
Type: Research Article
ISSN: 0954-0911

Keywords

Content available
Article
Publication date: 23 August 2011

375

Abstract

Details

Circuit World, vol. 37 no. 3
Type: Research Article
ISSN: 0305-6120

Article
Publication date: 1 February 1990

B.P. Richards, P. Burton and P.K. Footner

An investigation of the use of ultrasonic agitation for cleaning printed circuit boards using CFC‐based solvents has shown that, under the standard conditions required to produce…

Abstract

An investigation of the use of ultrasonic agitation for cleaning printed circuit boards using CFC‐based solvents has shown that, under the standard conditions required to produce clean assemblies, no damage will occur to the components studied. Damage can only be induced by use of anomalously longer times or higher power densities. In all cases in which damage has been induced, it is of a purely mechanical nature due to fatigue, and is located on the device bond‐wires and/or the package legs. Cleaning using CFC‐based solvents under standard ultrasonic conditions of power density and time etc. is readily achieved within 2 minutes, even with a minimum stand‐off height.

Details

Circuit World, vol. 16 no. 3
Type: Research Article
ISSN: 0305-6120

Article
Publication date: 1 January 1985

W. Canning Materials Ltd have announced the appointment of Mr W. E. I. Galloway as Managing Director with effect from 1st January, 1985. The Company is a leading manufacturer and…

Abstract

W. Canning Materials Ltd have announced the appointment of Mr W. E. I. Galloway as Managing Director with effect from 1st January, 1985. The Company is a leading manufacturer and supplier of industrial and speciality chemicals for the surface finishing industry.

Details

Circuit World, vol. 11 no. 2
Type: Research Article
ISSN: 0305-6120

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