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The purpose of this paper was to investigate how variations in the geometry of silicon chips and the presence of surface defects affect their static bending properties. By comparing the bending radius and strength across differently sized and treated chips, the study sought to understand the underlying mechanics that contribute to the flexibility of silicon-based electronic devices. This understanding is crucial for the development of advanced, robust and adaptable electronic systems that can withstand the rigors of manufacturing and everyday use.

This study explores the impact of silicon chip geometry and surface defects on flexibility through a multifaceted experimental approach. The methodology included preparing silicon chips of three distinct dimensions and subjecting them to thinning processes to achieve a uniform thickness verified via scanning electron microscopy (SEM). Finite element method (FEM) simulations and a series of four-point bending tests were used to analyze the bending flexibility theoretically and experimentally. The approach was comprehensive, examining both the intrinsic geometric factors and the extrinsic influence of surface defects induced by manufacturing processes.

The findings revealed a significant deviation between the theoretical predictions from FEM simulations and the experimental outcomes from the four-point bending tests. Rectangular-shaped chips demonstrated superior flexibility, with smaller dimensions leading to an increased bending strength. Surface defects, identified as critical factors affecting flexibility, were analyzed through SEM and atomic force microscopy, showing that etching processes could reduce defect density and enhance flexibility. Notably, the study concluded that surface defects have a more pronounced impact on silicon chip flexibility than geometric factors, challenging initial assumptions and highlighting the need for defect minimization in chip manufacturing.

This research contributes valuable insights into the design and fabrication of flexible electronic devices, emphasizing the significant role of surface defects over geometric considerations in determining silicon chip flexibility. The originality of the work lies in its holistic approach to dissecting the factors influencing silicon chip flexibility, combining theoretical simulations with practical bending tests and surface defect analysis. The findings underscore the importance of optimizing manufacturing processes to reduce surface defects, thereby paving the way for the creation of more durable and flexible electronic devices for future technologies.

This paper aims to realize the vertical interconnection in 3D radio frequency (RF) circuit by coaxial transitions with broad working bandwidth and small signal loss.

An advanced packaging method, 12-inch wafer-level through-mold-via (TMV) additive manufacturing, is used to fabricate a 3D resin-based coaxial transition with a continuous ground wall (named resin-coaxial transition). Designation and simulation are implemented to ensure the application universality and fabrication feasibility. The outer radius R of coaxial transition is optimized by designing and fabricating three samples.

The fabricated coaxial transition possesses an inner radius of 40 µm and a length of 200 µm. The optimized sample with an outer radius R of 155 µm exhibits S11 < –10 dB and S21 > –1.3 dB at 10–110 GHz and the smallest insertion loss (S21 = 0.83 dB at 77 GHz) among the samples. Moreover, the S21 of the samples increases at 58.4–90.1 GHz, indicating a broad and suitable working bandwidth.

The wafer-level TMV additive manufacturing method is applied to fabricate coaxial transitions for the first time. The fabricated resin-coaxial transitions show good performance up to the W-band. It may provide new strategies for novel designing and fabricating methods of RF transitions.

The aim of this study is to make a contribution towards reducing the deflections of silicon wafers. The deformation of silicon wafers used in the manufacture of electronic micro-components is one of the most common problems encountered by industrialists during manufacturing. Stack warping is typically produced during the process of depositing thin layers on a substrate. This is due to the thermal-mechanical stresses caused by the difference between the thermal expansion coefficients of the materials. Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models.

The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

This paper describes the influence of geometric modification on wafer deformation. The work show also the cruciality of stress reduction in the purpose to obtain less wafer deformation.

As it is known, the electrostatic discharge (ESD) protection design of integrated circuit is very important, among which the silicon controlled rectifier (SCR) is one of the most commonly used ESD protection devices. However, the traditional SCR has the disadvantages of too high trigger voltage, too low holding voltage after the snapback and longer turn-on time. The purpose of this paper is to design a high-performance SCR in accordance with the design window under 0.25 µm process, and provide a new scheme for SCR design to reduce the trigger voltage, improve the holding voltage and reduce the turn-on time.

Based on the traditional SCR, an RC-INV trigger circuit is introduced. Through theoretical analysis, TCAD simulation and tape-out verification, it is shown that RC-INV triggering SCR can reduce the trigger voltage, increase the holding voltage and reduce the turn-on time of the device on the premise of maintaining good robustness.

The RC-INV triggering SCR has great performance, and the test shows that the transmission line pulse curve with almost no snapback can be obtained. Compared with the traditional SCR, the trigger voltage decreased from 32.39 to 16.24 V, the holding voltage increased from 3.12 to 14.18 V and the turn-on time decreased from 29.6 to 16.6 ns, decreasing by 43.9% the level of human body model reached 18 kV+.

Under 0.25 µm BCD process, this study propose a high-performance RC-INV triggering SCR ESD protection device. The work presented in this paper has a certain guiding significance for the design of SCR ESD protection devices.

This study aims to perform the surface treatment of synthetic α-Fe₂O₃ red iron oxide pigment with hydrolysate 3-aminopropyl silane (A) and colloidal silica (CS) and investigate the effects of surface-treated pigment on the styrene acrylic (SA) emulsion and polyurethane (PU) dispersion.

For this purpose, firstly red iron oxide particles were modified with A and CS separately in an aqueous medium. After isolation of the modified iron oxide were characterized by Fourier transform infrared spectroscopy (FTIR), X-ray photoelectron spectroscopy (XPS) and scanning electron microscopy with energy dispersive spectroscopy (SEM-EDS). Moreover, the degree of the dispersion stability of the modified pigment in coatings with SA emulsion and PU dispersion was investigated by using an oscillation rheometer. Loss (G''), storage (G') modulus, loss factor [tan(δ)] and yield stress (τ⁰) values were determined by performing amplitude and frequency sweep tests.

The τ⁰ in SA coatings decreases with the amount of used A and increases with the amount of used CS. The τ⁰ decreases as the amount of used A and CS in PU coatings increases. The use of CS on red iron oxide pigments causes storage modulus to increase in SA coatings at low angular frequencies, while it causes a decrease in PU coatings.

To the best of the authors’ knowledge, for the first time, the suspended state of the iron oxide hybrid pigment formed with CS in the coating was investigated rheologically in this study.