Search results

This paper reports experiences gained in several research programmes, showing the necessity to develop improved environmental tests that better accelerate the mechanisms that degrade electronics. The tests specified in standards today do not consider relevant failure mechanisms. The paper describes the authors' philosophy for performing reliability testing. Examples of various reliability tests are given.

The transition to surface mounted device (SMD) technology in electronics manufacturing has placed new demands on the post‐solder cleaning process. For spacecraft electronic systems it is of the utmost importance that all flux residues be removed. This paper reports the results of an investigation of the impact of component stand‐off heights and the distance between solder joints on the cleaning process efficiency. The capability to clean beneath large chip carriers was evaluated for four different cleaning methods using isopropanol or CFC‐113 (Freon TMS) as cleaning liquid. The results show that the cleaning efficiency decreases considerably if the stand‐off height is less than 240 µm for 100 mil pitch chip carriers. For 50 mil pitch chip carriers the stand‐off height needs to be greater than 240 µm to achieve high cleaning efficiency. The cleaning efficiency beneath chip carriers with small stand‐off heights can be increased by using ultrasonic cleaning. However, a very thin layer of white residues is left where the flux has been removed if isopropanol is used as the cleaning liquid.

The purpose of this paper is to assess the effect of different temperature cycling profiles on the reliability of lead‐free 388 plastic ball grid array (PBGA) packages and to deeply understand crack initiation and propagation.

Temperature cycling of Sn‐3.8Ag‐0.7Cu PBGA packages was carried out at two temperature profiles, the first ranging between −55°C and 100°C (TC1) and the second between 0°C and 100°C (TC2). Crack initiation and propagation was analyzed periodically and totally 7,000 cycles were run for TC1 and 14,500 for TC2. Finite element modeling (FEM), for the analysis of strain and stress, was used to corroborate the experimental results.

The paper finds that TC1 had a characteristic life of 5,415 cycles and TC2 of 14,094 cycles, resulting in an acceleration factor of 2.6 between both profiles. Cracks were first visible for TC1, after 2,500 cycles, and only after 4,000 cycles for TC2. The crack propagation rate was faster for TC1 compared to TC2, and faster at the package side compared to the substrate side. The difference in crack propagation rate between the package side and substrate side was much larger for TC1 compared to TC2. Cracks developed first at the package side, and were also larger compared to the substrate side. The Cu tracks on the substrate side affected the crack propagation sites and behaved as SMD. All cracks propagated through the solder and crack propagation was mainly intergranular. Crack propagation was very random and did not follow the distance to neutral point (DNP) theory. FEM corroborated the experimental results, showing both the same critical location of highest creep strain and the independence of DNP.

Such extensive work on the reliability assessment of Pb‐free 388 PBGA packages has never been performed. This work also corroborates the results from other studies showing the difference in behavior between Pb‐free and Pb‐containing alloys.

This paper aims to describe some of the European Space Agency (ESA) workmanship standards which are based on industrial practices. Coordination with National Aeronautics and Space Administration (NASA) Centres on workmanship issues is also to be described.

The first ESA (then ESRO) workmanship standard was published in 1972. It applied to the hand soldering of electronic assemblies and became a contractual document, either replacing, or supplementing a vast number of company standards that had existed in European manufacturing companies. Since then some 40 standards related to Materials and Processes have been developed by ESA, the majority of which are to be found in the European Cooperation for Space Standardization (ECSS) series of European standards.

It is shown that, where appropriate, the standards are backed by a number of ESA‐approved skills training schools which provide training courses that result in the certification of operators, inspectors and instructors.

The workmanship standards are periodically revised in order to take into account newly developed technologies, the results of failure analyses (lessons learnt), laboratory and field test results, as well as some particular requests from industry.

The purpose of this paper is to present the development and implementation of a system of test methods for determining the contamination level in cleaning baths and using this system for long‐term monitoring in printed circuit board (PCB) production.

A set of test methods was chosen that indicated the contamination of production cleaning baths in four chambers of an ultrasonic cleaning equipment filled with a commercial alkaline cleaner and isopropanol. By long‐term monitoring, the amount of mechanical impurities, residue‐on‐evaporation, pH and conductivity were measured. Depending on the contamination of the cleaning baths, the final contamination of PCB surfaces was predicted and the baths were replaced with fresh baths.

A novel system for testing and monitoring the contamination of cleaning baths was developed and implemented. The sustainable compliance with the specification was assured in PCB production, thus, the final PCB contamination achieved was under 1.5/1.2 μg NaCl/cm² as measured using the IPC‐TM‐650 test method. Quality requirements were fulfilled. This novel system was successfully integrated into the company's quality management system.

The set of test methods were used for an alkaline cleaner and isopropanol and for both a conventional solder and a lead‐free one. Because the course of bath contamination, monitored by the four test methods, was found to be proportional, further development should be focused on the issue – i.e. to determine if the “proportionality” would be universal for all types of PCB manufacturing.

The paper deals with a new approach for quality testing and assurance in PCB manufacturing. A set of test methods for monitoring contamination levels in production cleaning baths was implemented. This also supports process control and minimises the impact of cleaning processes on the environment (i.e. the production of waste from cleaning was reduced).

This paper aims to investigate the effect of no-clean flux chemistry with various weak organic acids (WOAs) as activators on the corrosion reliability of electronics with emphasis on the hygroscopic nature of the residue.

The hygroscopicity of flux residue was studied by quartz crystal microbalance, while corrosive effects were studied by leakage current and impedance measurements on standard test boards. The measurements were performed as a function of relative humidity (RH) in the range from 60 to ∼99 per cent at 25°C. The corrosiveness of solder flux systems was visualized by the ex situ analysis using a gel with tin ion indicator.

The results showed that the solder flux residues are characterized by different threshold RH, above which a sudden increase in direct current leakage by 2–4 orders of magnitude and a significant reduction in surface resistance in the impedance measurements were observed.

The findings are attributed to the deliquescence RH of the WOA(s) in the flux and chemistry of water-layer formation. The results show the importance of WOA type in relation to its solubility and deliquescence RH on the corrosion reliability of printed circuit boards under humid conditions.

The classification of solder flux systems according to IPC J-STD-004 standard does not specify the WOAs in the flux; however, ranking of the flux systems based on the hygroscopic property of activators would be useful information when selecting no-clean flux systems for electronics with applications in humid conditions.

The purpose of this paper is to present a new test method (tape peel method) to evaluate conformal coating adhesion to electronic assemblies.

The key issue for this method is the low cohesive force of conformal coatings, and hence selection of a supporting material to peel the coating from the substrate is critical. A suitable cloth material (35 per cent cotton +75 per cent polyester with 20 per cent open area) has been selected as a peel tape, and achieved the best bonding with coatings, and the smallest affect on the coating curing process. Using the tape, the peel force of the coating from the electronic assembly, can be measured quantitatively, and hence the adhesion performance of the conformal coating assessed.

The method was validated using different coating types, substrate materials (bare laminate with and without resist, copper clad laminate, and contaminated laminate material), assemblies and components. The results demonstrated that the tape peel test is a sensitive method for measuring coating adhesion on different materials found on PCB assemblies. Coating adhesion was found not to be effected by a wide range flux residues, but components and some resists presented a far greater coating challenge, with some coatings achieving very low adhesion values.

This new method for evaluating conformal coating adhesion to electronic assemblies will be of benefit to coating developers and users, and help to minimise adhesion failures in service. The test has been demonstrated to be sensitive to a number of process and material variables.

This paper aims to present a machine learning framework for using big data analytics to predict the reliability of solder joints. The purpose of this study is to accurately predict the reliability of solder joints by using big data analytics.

A machine learning framework for using big data analytics is proposed to predict the reliability of solder joints accurately.

A machine learning framework for predicting the life of solder joints accurately has been developed in this study. To validate its accuracy and efficiency, it is applied to predict the long-term reliability of lead-free Sn96.5Ag3.0Cu0.5 (SAC305) for three commonly used surface finishes such OSP, ENIG and IAg. The obtained results show that the predicted failure based on the machine learning method is much more accurate than the Weibull method. In addition, solder ball/bump joint failure modes are identified based on various solder joint failures reported in the literature.

The ability to predict thermal fatigue life accurately is extremely valuable to the industry because it saves time and cost for product development and optimization.

The aim of this work was to investigate which parameters affect the long‐term performance of coil coated galvanised steel sheet. Therefore, the paint adhesion and corrosion resistance of selected painted pre‐treated galvanised steel substrates were studied. The systems investigated included chromate‐free pre‐treatments and primers. The polymer coated panels were tested by using: T‐bend, combined cross cut and adhesion, prohesion and QUV‐A tests. The surface energy of the painted panels was determined by contact angle measurements and outdoor testing of the panels was also initiated. The test results showed that the primer was the most important parameter for painted metal alloy coated steel, but the long‐term performance of the system also depends on the compatibility of all four layers, i.e. substrate, pre‐treatment, primer and topcoat.

Surface mount technology (SMT) is widely used and plays an important role in electronic equipment. The purpose of this paper is to reveal the effects of interface cracks on the fatigue life of SMT solder joint under service load and to provide some valuable reference information for improving service reliability of SMT packages.

A 3D geometric model of SMT package is established. The mechanical properties of SMT solder joint under thermal cycling load and random vibration load were solved by 3D finite element analysis. The fatigue life of SMT solder joint under different loads can be calculated by using the modified Coffin–Manson model and high-cycle fatigue model.

The results revealed that cracks at different locations and propagation directions have different effect on the fatigue life of the SMT solder joint. From the location of the cracks, Crack 1 has the most significant impact on the thermal fatigue life of the solder joint. Under the same thermal cycling conditions, its life has decreased by 46.98%, followed by Crack 2, Crack 4 and Crack 3. On the other hand, under the same random vibration load, Crack 4 has the most significant impact on the solder joint fatigue life, reducing its life by 81.39%, followed by Crack 1, Crack 3 and Crack 2. From the crack propagation direction, with the increase of crack depth, the thermal fatigue life of the SMT solder joint decreases sharply at first and then continues to decline almost linearly. The random vibration fatigue life of the solder joint decreases continuously with the increase of crack depth. From the crack depth of 0.01 mm to 0.05 mm, the random vibration fatigue life decreases by 86.75%. When the crack width increases, the thermal and random vibration fatigue life of the solder joint decreases almost linearly.

This paper investigates the effects of interface cracks on the fatigue life and provides useful information on the reliability of SMT packages.