Multichip Module Designs for High Performance Applications
C. Neugebauer
(GE Corporate Research and Development, Schenectady, New York, USA)
R.O. Carlson
(GE Corporate Research and Development, Schenectady, New York, USA)
R.A. Fillion
(GE Corporate Research and Development, Schenectady, New York, USA)
T.R. Haller
(GE Corporate Research and Development, Schenectady, New York, USA)
42
Abstract
A package performance bottleneck is developing because of the inability to densely wire single chip modules together on the printed wiring board. An array processor, constructed by means of various high performance packaging techniques, demonstrates that multichip modules of even modest size can give dramatic improvements in the packaging figure of merit.
Citation
Neugebauer, C., Carlson, R.O., Fillion, R.A. and Haller, T.R. (1990), "Multichip Module Designs for High Performance Applications", Microelectronics International, Vol. 7 No. 1, pp. 28-32. https://doi.org/10.1108/eb044399
Publisher
:MCB UP Ltd
Copyright © 1990, MCB UP Limited