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Business process workflow is a design conceptualization to automate the sequence of activities to achieve a business goal with involved participants and a predefined set of rules. Regarding this, a formal business workflow model is a prime requisite to implement a consistent and rigorous business process. In this context, majority of the existing research works are formalized structural features and have not focused on functional and behavioral design aspects of business processes. To address this problem, this paper aims to propose a formal model of business process workflow called as business process workflow using typed attributed graph (BPWATG) enriched with structural, functional and behavioral characteristics of business processes.

Typed attributed graph (ATG) and first-order logic have been used to formalize proposed BPWATG to provide rigorous syntax and semantics towards business process workflows. This is an effort to execute a business workflow on an automated machine. Further, the proposed BPWATG is illustrated using a case study to show the expressiveness of proposed model. Besides, the proposed graph is initially validated using generic modelling environment (GME) case tool. Moreover, a comparative study is performed with existing formal approaches based on several crucial features to exhibit the effectiveness of proposed BPWATG.

The proposed model is capable of facilitating structural, functional and behavioral aspects of business process workflows using several crucial features such as dependency conceptualization, timer concepts, exception handling and deadlock detection. These features are used to handle real-world problems and ensure the consistency and correctness of business workflows.

BPWATG is proposed to formalize a business workflow that is required to make a model of business process machine-readable. Besides, formalizations of dependency conceptualization, exception handling, deadlock detection and time-out concepts are specified. Moreover, several non-functional properties (reusability, scalability, flexibility, dynamicity, reliability and robustness) are supported by the proposed model.

Increase in the speed of processors has led to crucial role of communication in the performance of systems. As a result, routing is taken into consideration as one of the most important subjects of the network-on-chip (NOC) architecture. Routing algorithms to deadlock avoidance prevent packets route completely based on network traffic condition by means of restricting the route of packets. This action leads to less performance especially in non-uniform traffic patterns. On the other hand, true fully adaptive routing algorithm provides routing of packets completely based on traffic conditions. However, deadlock detection and recovery mechanisms are needed to handle deadlocks. Use of a global bus beside NOC as a parallel supportive environment provides a platform to offer advantages of both features of bus and NOC.

In this research, the authors use this bus as an escaping path for deadlock recovery technique.

According to simulation results, this bus is a suitable platform for a deadlock recovery technique.

This bus is useful for broadcast and multicast operations, sending delay sensitive signals, system management and other services.

Multi-robot coalition formation (MRCF) refers to the formation of robot coalitions against complex tasks requiring multiple robots for execution. Situations, where the robots have to participate in multiple coalitions over time due to a large number of tasks, are called Time-extended MRCF. While being NP-hard, time-extended MRCF also holds the possibility of resource deadlocks due to any cyclic hold-and-wait conditions among the coalitions. Existing schemes compromise on solution quality to form workable, deadlock-free coalitions through instantaneous or incremental allocations.

This paper presents an evolutionary algorithm (EA)-based task allocation framework for improved, deadlock-free solutions against time-extended MRCF. The framework simultaneously allocates multiple tasks, allowing the robots to participate in multiple coalitions within their schedule. A directed acyclic graph–based representation of robot plans is used for deadlock detection and avoidance.

Allowing the robots to participate in multiple coalitions within their schedule, significantly improves the allocation quality. The improved allocation quality of the EA is validated against two auction schemes inspired by the literature.

To the best of the author's knowledge, this is the first framework which simultaneously considers multiple MR tasks for deadlock-free allocation while allowing the robots to participate in multiple coalitions within their plans.

Deadlock is a rather undesirable phenomenon and must be well solved in flexible manufacturing systems (FMS). This paper aims to propose a general iterative deadlock control method for a class of generalized Petri nets (GPN), namely, G-systems, which can model an FMS with assembly and disassembly operations of multiple resource acquisition. When given an uncontrolled G-system prone to deadlocks, the work focuses on the synthesis of a near-optimal, non-blocking supervisor based on reachability graph (RG) analysis.

The concept of a global idle place (GIP) for an original uncontrolled G-system is presented. To simplify the RG computation of an uncontrolled G-system, a GIP is added temporarily to the net model during monitor computation steps. Starting with one token and then by gradually increasing the number of tokens in the GIP at each iteration step, the related net system is obtained. The minimal-covered-set of all bad markings of the related net system suffering from deadlock can be identified and then removed by additional monitors through an established place-invariant control method. Consequently, all related systems are live, and the GIP is finally removed when the non-blockingness of the controlled system is achieved. Meanwhile, the redundancy of monitors is also checked.

A typical G-system example is provided to demonstrate the applicability and effectiveness of the proposed method. Experiments show that the proposed method is easy to use and provides very high behavioral permissiveness for G-system. Generally, it can achieve an optimal or a near-optimal solution of the non-blocking supervisor.

In this work, the concept of GIP for G-systems is presented for synthesis non-blocking supervisors based on RG analysis. By using GIP, an effective deadlock control method is proposed. Generally, the proposed method can achieve an optimal or a near-optimal, non-blocking supervisor for an uncontrolled G-system prone to deadlocks.

Siphon-based deadlock control in a flexible manufacturing system (FMS) suffers from the problems of computational and structural complexity since the number of siphons grows exponentially with respect to the size of its Petri net model. In order to reduce structural complexity of a supervisor, a set of elementary siphons derived from all strict minimal siphons (SMS) is explicitly controlled. The purpose of this paper is through fully investigating the structure of a class of generalized Petri nets, WS3PR, to compute all SMS and a compact set of elementary siphons.

Based on graph theory, the concepts of initial resource weighted digraphs and restricted subgraphs are proposed. Moreover, the concept of augmented siphons is proposed to extend the application of elementary siphons theory for WS3PR. Consequently, the set of elementary siphons obtained by the proposed method is more compact and well suits for WS3PR.

In order to demonstrate the proposed method, an FMS example is presented. All SMS and elementary siphons can be derived from initial resource weighted digraphs. Compared with those obtained by the method in Li and Zhou, the presented method is more effective to design a structural simple liveness-enforcing supervisor for WS3PR.

This work presents an effective method of computing SMS and elementary siphons for WS3PR. Monitors are added for the elementary siphons only, and the controllability of every dependent siphon is ensured by properly supervising its elementary ones. A same set of elementary siphons can be admitted by different WS3PR with isomorphic structures.

Public services can be modelled, analysed and implemented using notations and tools for the business process (BP) abstraction. Applying such an explicit approach public administrations (PAs) can better react to the undergoing transformation in service provisioning and they can continuously improve service quality in order to satisfy citizens and business requests, while coping with decreasing budgets. The purpose of this paper is to discuss these issues.

The proposed approach relies on using formal methods, in particular unfolding to analyse the correctness of BP. The paper also compares and selects mapping rules from semi-formal to formal modelling languages; these techniques are presented in the context of the BP Modelling Languages and Petri Net (PN).

Main aim of this paper is to raise the need for formal verification of BP governing the interactions among PAs, which more and more need to be supported by ICT mechanisms, and then are not so much tolerant to errors and imperfections in the process specification. The paper illustrates the main motivations of such a work and it introduces a verification technique of a BP using a mapping of a high-level notation (such as BPMN 2.0) to a formal notation (such as PNs) for which formal analysis techniques can be adopted. In particular the verification step is implemented using an unfolding-based technique.

The paper answers a call for further development of the body of knowledge on effective analysis of BPs, a rapidly emerging field of interest for large and ultra large scenarios, where a clear gap in literature exists. Than the paper shows that formal techniques are mature enough to be applied on real scenarios.

The small area network for data communication within routers is suffering from storage of packet, throughput, latency and power consumption. There are a lot of solutions to increase speed of commutation and optimization of power consumption; one among them is Network-on-chip (NoC). In the literature, there are several NoCs which can reconfigurable dynamically and can easily test and validate the results on FPGA. But still, NoCs have limitations which are regarding chip area, reconfigurable time and throughput.

To address these limitations, this research proposes the dynamically buffered and bufferless reconfigurable NoC (DB2R NoC) using X-Y algorithm for routing, Torus for switching and Flexible Direction Order (FDOR) for direction finding between source and destination nodes. Thus, the 3 × 3 and 4 × 4 DB2R NoCs are made free from deadlock, low power and latency and high throughput. To prove the applicability and performance analysis of DB2R NoC for 3 × 3 and 4 × 4 routers on FPGA, the 22 bits for buffered and 19 bit for bufferless designs have been successfully synthesized using Verilog HDL and implemented on Artix-7 FPGA development bond. The virtual input/output chips cope pro tool has been incorporated in the design to verify and debug the complete design on Artix-7 FPGA.

In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.

In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.

The lack of reference architecture for Internet of Things (IoT) modeling impedes the successful design and implementation of an IoT-based production logistics and supply chain system (PLSCS). The authors present this study in two parts to address this research issue. Part A proposes a unified IoT modeling framework to model the dynamics of distributed IoT processes, IoT devices, and IoT objects. The models of the framework can be leveraged to support the implementation architecture of an IoT-based PLSCS. The second part (Part B) of this study extends the discussion of implementation architecture proposed in Part A. Part B presents an IoT-based cyber-physical system framework and evaluates its performance. The paper aims to discuss this issue.

This paper adopts a design research approach, using ontology, process analysis, and Petri net modeling scheme to support IoT system modeling.

The proposed IoT system-modeling approach reduces the complexity of system development and increases system portability for IoT-based PLSCS. The IoT design models generated from the modeling can also be transformed to implementation logic.

The proposed IoT system-modeling framework and the implementation architecture can be used to develop an IoT-based PLSCS in the real industrial setting. The proposed modeling methods can be applied to many discrete manufacturing industries.

The IoT modeling framework developed in this study is the first in this field which decomposes IoT system design into ontology-, process-, and object-modeling layers. A novel implementation architecture also proposed to transform above IoT system design models into implementation logic. The developed prototype system can track product and different parts of the same product along a manufacturing supply chain.

A survey of current work on database systems is presented. The area is divided into three main sectors: data models, data languages and support for database operations. Data models are presented as the link between the database and the real world. Languages range from formal algebraic languages to attempts to use a dialogue in English to formulate queries. The support includes hardware for content addressing, database machines and software techniques for optimizing and evaluating group expressions. Mathematical models are used to organize this support. Throughout there is a tutorial component and evaluation, which in both cases is related to the application of database ideas to documentation.

The purpose of this paper is twofold. In view of the importance of process platform‐based production configuration (PPbPC) in sustaining product family production efficiency, it is to study the underlying logic for configuring production processes for a product family based on a process platform. Second, it is to apply the Petri nets (PNs) techniques to model PPbPC, in attempting to shed light on the underlying logic.

The authors first identify the fundamental issues in PPbPC, including variety handling, process variation accommodation, configuration at different abstraction levels, and constraint satisfaction. To accommodate the corresponding modelling difficulties, the authors develop a formalism of hierarchical colored timed PNs (HCTPNs) based on the principles of hierarchical PNs, timed PNs, and colored PNs. In the formalism, three types of nets together with a system of HCTPNs are defined to address the modelling of PPbPC.

Applying HCTPNs to vibration motors' case has revealed the logic of specifying complete production processes of final products at different levels of abstraction to achieve production configuration. The preliminary results also further demonstrate the feasibility of modelling PPbPC based on HCTPNs.

Traditional approaches to planning production processes for individual products may limit production performance improvement when companies need to timely produce a high variety of customized products. Systematic methods should be developed to plan production processes for product families so as to achieve production efficiency while utilizing the existing manufacturing resources.

By integrating the advantages of existing PN techniques, the HCTPNs formalism is developed to shed light on planning production processes for product families. The resulting production configuration model can facilitate practitioners to achieve production efficiency in producing large numbers of customized products.