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After a brief introduction to the advantages and method of construction of flip chip solder bond devices, this paper looks at different techniques that can be used to inspect these devices at various stages in their construction. These techniques include optical, infra‐red, acoustic and electron microscopy, radiograph, electrical and tensile testing. The advantages and limitations of each of the techniques are discussed and an outline inspection schedule is suggested.

A measurement tool, capable of monitoring misalignment of layers in multilayer printed circuit boards, is described. Its uses, limitations and its advantages for use in SPC and reliability predictions are highlighted.

The benefits of the thin film multichip module (MCM‐D) approach to high density packaging for VLSI devices have now been amply demonstrated by a number of research groups. The successful emergence of a viable multichip module industry from this research base will, however, depend upon the installation of an industry‐wide manufacturing infrastructure. This will have to provide the necessary range of concurrent design capabilities, make pretested bare die available, and include multichip module vendors who can offer an integrated capability in module design, substrate layout and manufacture, advanced module assembly, packaging and test. Each of these areas of MCM‐D technology merits detailed attention in its own right, sufficient to justify many individual papers and presentations. This present paper focuses on just one of these topics and addresses the approach taken by GEC Plessey Semiconductors (GPS) to the development and control of a highly manufacturable MCM‐D silicon substrate process. The GPS ‘Process I’ four‐layer metal, aluminium‐polyimide substrate technology is described, the technology development and process control test structures are detailed and process characterisation data presented.

The hermetically sealed ceramic chip carrier package and the plastic small outline (SO) IC package are both now widely used in hybrid microelectronics. These packages are currently being applied with other discrete surface mount devices to PWB technology in order to increase circuit density and reduce weight. This paper discusses the evaluation of two soldering techniques for the attachment of the chip carrier and SOIC packages to epoxy glass PWBs: the first by solder cream printing or pretinning of the circuit board and subsequent attachment by solder reflow, and the second by a novel jet soldering technique. The thermally induced expansion mismatch between epoxy glass and ceramic chip carriers and the strain induced fatigue this causes in the solder joints are now well documented, and results are presented for the effects of temperature cycling ceramic chip carriers soldered onto PWBs. Various PWB materials have been assessed including FR4, elastomer coated FR4, polyimide kevlar, and epoxy glass laminated copper clad invar. Reliability of these assemblies is discussed in terms of the appearance of micro‐cracks in the solder fillets and the occurrence of electrical discontinuity in the solder joints during temperature cycling.

The relentless drive towards greater complexity and interconnection density on silicon integrated circuit (SIC) devices is leading to a reappraisal of techniques for making electrical connections from the SIC to the next level of packaging. The techniques being examined include fine pitch Wire Bonding, Tape Automated Bonding (TAB) and Flip‐chip Solder Bonding. This latter technique forms the subject of this paper. The history of flip‐chip solder bonding technology is briefly reviewed and metallurgical, physical and mechanical aspects of the bonding process and of the resulting joints are discussed. The merits of the flip‐chip bonding process are indicated and applications examples presented. Particular attention is given to the fabrication of a novel pyroelectric‐SIC thermal imaging sensor using flip‐chip solder bonding.

This chapter seeks to explain how lesson study can contribute to the growth of teacher expertise, enabling the participants to work together to address the complexity of teaching and grow what we call ‘pedagogic literacy’, a holistic but incomplete glimpse of what it means to be a teacher. The model proposed is not complete and cannot be complete given the endless complexity of the classroom. Lesson study, we conclude, is a vehicle for enabling teachers to grow their understanding of teaching and learning, while drawing on a complex web of underpinning interconnected dimensions that teachers develop throughout the varied stages of their careers.

A new lass of sensors for thermal imaging and detection in the infra‐red band is emerging which exploits the pyroelectric effect in ferroelectric materials. These sensors, which are fabricated in the form of large linear or two‐dimensional arrays of detectors interfaced to a silicon readout circuit, do not require cooling for their operation, in contrast to the photon detection based thermal imagers. They thus have the potential for low cost thermal detection and imaging. This paper examines the design of these arrays and the technologies employed in their fabrication, with particular attention to their specialised packaging requirements, by reference to a range of linear and two‐dimensional pyroelectric array devices that have been fabricated in this laboratory.

This chapter explores the use of Lesson Study (LS) as a strategy for co-constructing pedagogical knowledge and draws on data from a series of interviews with student teachers. Sixteen student teachers, undertaking a postgraduate teacher training program in higher education in England, engaged in LS as an official assessment of their ability to jointly plan, deliver, and evaluate a lesson. LS is thus seen to promote an intense collaborative working relationship between participating student teachers that engenders fresh opportunities for learning. It is argued, then, that this approach can challenge the prevalent model of individually led professional development by facilitating a space for the co-construction of pedagogical knowledge. LS is also explored for its potential to bridge the theory-practice divide by enabling participant student teachers to generate theory from practice.

The screen printing and reflowing of solder paste is compared with wave soldering for the attachment of surface mounted devices to PCBs. Both techniques have advantages and disadvantages which are fully discussed. The method chosen for a particular application will depend upon the production facilities available, the principal package types involved in the design, and the anticipated cost. The main advantages of the screen printing process have been found to be a relatively low soldering temperature, freedom from device orientation and package design constraints, and few proximity effects, while those for the wave soldering process have been found to be compatibility with present mass soldering operations, the ability to combine both through‐hole devices and SMDs on the same board, a single soldering operation, and a solder joint volume defined by the joint design. It is concluded that in the long term screen printing and reflow is likely to become the dominant technology, but in the intermediate term wave soldering is likely to remain attractive while manufacturers move from the established through‐hole technology to the more space‐efficient surface mounted technology.

The problems associated with the direct attachment of leadless ceramic chip carriers (LCCCs) to conventional PWB structures subjected to ambient thermal and power (on/off) cycling are now widely documented. The reliability of LCCCs mounted on various novel substrate materials has been assessed here during ambient thermal cycling from −55° to 125°C and −20° to +70°C and during power heat cycling. Polyimide Kevlar material was rejected on the basis that microcracks, formed in the laminate during thermal cycling, propagated to the surface and resulted in copper track breakages. A flexible laminate interconnection structure for strain relief was found to be too cumbersome for most applications and gave only a small reliability improvement. Polyimide quartz and copper‐invar‐copper cored materials were both found to give a high degree of reliability in thermal cycling. The metal cored laminate is preferred because it is also a more rigid structure with the better thermal conductance needed for many high performance and reliability applications. An elastomer coated FR4 material also performed well during lower temperature thermal and power cycling tests and represents a reduced cost option for less severe environments.