A hybrid of WOA and mGWO algorithms for global optimization and analog circuit design automation

Abstract

Purpose

This paper aims to resolve the sizing issues of analog circuit design by using proposed metaheuristic optimization algorithm.

Design/methodology/approach

The hybridization of whale optimization algorithm and modified gray wolf optimization (WOA-mGWO) algorithm is proposed, and the same is applied for the automated design of analog circuits.

Findings

The proposed hybrid WOA-mGWO algorithm demonstrates better performance in terms of convergence rates and average fitness of the function after testing it with 23 classical benchmark functions. Moreover, a rigorous performance evaluation is done with 20 independent runs using Wilcoxon rank-sum test.

Practical implications

For evaluating the performance of the proposed algorithm, a conventional two-stage operational amplifier is considered. The aspect ratios calculated by simulating the algorithm in MATLAB are later used to design the operational amplifier in Cadence environment using 180nm CMOS standard process.

Originality/value

The hybrid WOA-mGWO algorithm is tailored to improve the exploration ability of the algorithm by combining the abilities of two metaheristic algorithms, i.e. whale optimization algorithm and modified gray wolf optimization algorithm. To build further credence and to prove its profound existence in the latest state of the art, a statistical study is also conducted over 20 independent runs, for the robustness of the proposed algorithm, resulting in best, mean and worst solutions for analog IC sizing problem. A comparison of the best solution with other significant sizing tools proving the efficiency of hybrid WOA-mGWO algorithm is also provided. Montecarlo simulation and corner analysis are also performed to validate the endurance of the design.

Citation

Majeed, M.A.M. and Patri, S.R. (2019), "A hybrid of WOA and mGWO algorithms for global optimization and analog circuit design automation", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 38 No. 1, pp. 452-476. https://doi.org/10.1108/COMPEL-04-2018-0175