Search results

This paper aims to investigate the printability of photocurable PDMS with digital light processing (DLP) in terms of dimensional accuracy, mechanical properties, isotropy and postcure shrinkage.

The photocurable PDMS was made from methacrylated PDMS-macromer and 2,4,6-Trimethylbenzoyldi-Phenylphosphinate (TPO-L) photoinitiator. The PDMS was printed using different orientations, sizes and post-exposure conditions and then evaluated by tensile test and microscope to determine the printability.

Printed parts show good accuracy and low shrinkage, but high directionality in modulus, ductility and strength. The dimensional error is less than 2% and the shrinkage rates are less than 0.52%. In contrast, the modulus varies between 0.87 and 0.96 MPa depending on print orientation, elongation varies from 34.7% to 66.4% and strength varies from 0.23 to 0.49 MPa.

This study quantitatively characterizes the printability of photo curable PDMS with DLP, which has not been reported elsewhere. This paper also discusses the challenges of PDMS printing for future advancement.

3D chip stacking is a key technology for 3D integration in which two or more chips are stacked with vertical interconnections. In the case of multi chip stacking with fine pitch microbump connections, capillary dispensing presents big limitations in terms of cost and processability. The purpose of this paper is to describe the way in which wafer‐level underfill (WLUF) process development was carried out with particular emphasis on microbump height coplanarity, bonding pressure distribution and the alignment of the microbumps. A three factorial design of experiment (DOE) was also conducted to enhance the understanding of the factors impacting the WLUF process such as bonding pressure, temperature and time on reliability test.

B‐staged WLUF was laminated on an 8″ wafer with a 30 μm pitch bump structure of 8 μm Cu/5 μm Sn2.5Ag Pb‐free solder. After wafer dicing, the chip with the WLUF was assembled on a substrate chip with the same bump structure using a high accuracy bonder. The substrate chip had metalisation (wiring) to enable evaluation of the electrical characteristics of the bonded daisy chain chips as they varied with material bonding process conditions and reliability testing.

The WLUF bonding process development pertaining to the processability and reliability for the flip chip assembly using Cu/SnAg microbumps was successful in this work.

The development of a WLUF bonding process that offers reliability for flip chip assembly using Cu/SnAg microbumps has been presented in this work. The critical steps, such as alignment of the WLUF coated chip with the substrate chip and void elimination, which enable this technology to work were optimised.