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An earlier article in this journal outlined a model of the process of negotiation with particular reference to negotiation in the industrial relations context. The model suggests that negotiations go through five phases or patterns of negotiating activity as the negotiators move through to a settlement. On the basis of the model, it is possible to identify several implications for negotiators, and, in particular, to make the point that the two parties must jointly manage their progress through the negotiations. Within the negotiation process there are three potential deadlocks which could emerge to obstruct this progress if the negotiations were not properly and jointly managed. This article develops the concept of deadlocks in negotiation more fully, and attempts to identify the implications for negotiators by suggesting how deadlocks might be identified and overcome.

Increase in the speed of processors has led to crucial role of communication in the performance of systems. As a result, routing is taken into consideration as one of the most important subjects of the network-on-chip (NOC) architecture. Routing algorithms to deadlock avoidance prevent packets route completely based on network traffic condition by means of restricting the route of packets. This action leads to less performance especially in non-uniform traffic patterns. On the other hand, true fully adaptive routing algorithm provides routing of packets completely based on traffic conditions. However, deadlock detection and recovery mechanisms are needed to handle deadlocks. Use of a global bus beside NOC as a parallel supportive environment provides a platform to offer advantages of both features of bus and NOC.

In this research, the authors use this bus as an escaping path for deadlock recovery technique.

According to simulation results, this bus is a suitable platform for a deadlock recovery technique.

This bus is useful for broadcast and multicast operations, sending delay sensitive signals, system management and other services.

Deadlock is a rather undesirable phenomenon and must be well solved in flexible manufacturing systems (FMS). This paper aims to propose a general iterative deadlock control method for a class of generalized Petri nets (GPN), namely, G-systems, which can model an FMS with assembly and disassembly operations of multiple resource acquisition. When given an uncontrolled G-system prone to deadlocks, the work focuses on the synthesis of a near-optimal, non-blocking supervisor based on reachability graph (RG) analysis.

The concept of a global idle place (GIP) for an original uncontrolled G-system is presented. To simplify the RG computation of an uncontrolled G-system, a GIP is added temporarily to the net model during monitor computation steps. Starting with one token and then by gradually increasing the number of tokens in the GIP at each iteration step, the related net system is obtained. The minimal-covered-set of all bad markings of the related net system suffering from deadlock can be identified and then removed by additional monitors through an established place-invariant control method. Consequently, all related systems are live, and the GIP is finally removed when the non-blockingness of the controlled system is achieved. Meanwhile, the redundancy of monitors is also checked.

A typical G-system example is provided to demonstrate the applicability and effectiveness of the proposed method. Experiments show that the proposed method is easy to use and provides very high behavioral permissiveness for G-system. Generally, it can achieve an optimal or a near-optimal solution of the non-blocking supervisor.

In this work, the concept of GIP for G-systems is presented for synthesis non-blocking supervisors based on RG analysis. By using GIP, an effective deadlock control method is proposed. Generally, the proposed method can achieve an optimal or a near-optimal, non-blocking supervisor for an uncontrolled G-system prone to deadlocks.

Multi-robot coalition formation (MRCF) refers to the formation of robot coalitions against complex tasks requiring multiple robots for execution. Situations, where the robots have to participate in multiple coalitions over time due to a large number of tasks, are called Time-extended MRCF. While being NP-hard, time-extended MRCF also holds the possibility of resource deadlocks due to any cyclic hold-and-wait conditions among the coalitions. Existing schemes compromise on solution quality to form workable, deadlock-free coalitions through instantaneous or incremental allocations.

This paper presents an evolutionary algorithm (EA)-based task allocation framework for improved, deadlock-free solutions against time-extended MRCF. The framework simultaneously allocates multiple tasks, allowing the robots to participate in multiple coalitions within their schedule. A directed acyclic graph–based representation of robot plans is used for deadlock detection and avoidance.

Allowing the robots to participate in multiple coalitions within their schedule, significantly improves the allocation quality. The improved allocation quality of the EA is validated against two auction schemes inspired by the literature.

To the best of the author's knowledge, this is the first framework which simultaneously considers multiple MR tasks for deadlock-free allocation while allowing the robots to participate in multiple coalitions within their plans.

This paper aims to propose and formulate a complicated routing/scheduling problem for multiple automated guided vehicles (AGVs) in a manufacturing system.

Considering the due date of AGVs requiring for material handling among shops in a jobshop layout, their earliness and tardiness are significant in satisfying the expected cycle time and from an economic view point. Therefore, the authors propose a mathematical program to minimize the penalized earliness and tardiness for a conflict-free and just-in-time production.

The model considers a new concept of turning point for deadlock resolution. As the mathematical program is difficult to solve with a conventional method, an optimization method in two stages, namely, searching the solution space and finding optimal solutions are proposed. The performance of the proposed mathematical model is tested in a numerical example.

A case study in real industrial environment is conducted. The findings lead the decision-makers to develop a user interface decision support as a simulator to plan the AGVs’ movement through the manufacturing network and help AGVs to prevent deadlock trap or conflicts. The proposed decision support can easily be commercialized.

The benefits of such commercialization are increase in the quality of material handling, improve the delivery time and prevent delays, decrease the cost of traditional handling, capability of computerized planning and control, intelligent tracking and validation experiments in simulation environment.

The purpose of this study is to investigate the benefits of the turning point layout; a simulation model being applicable for strategic level is designed that compares systems with and without turning points. Specifically, the avoidance of deadlocks and prevention of conflicts is substantial.

Optimization process for different layouts and configuration of autonomous guided vehicles (AGVs) are worked out using statistical methods for design parameters. Regression analysis is used to find effective design parameters and analysis of variance is applied for adjusting critical factors. Also, the optimal design is then implemented in a manufacturing system for an industrial automation and the results are reported.

The outputs imply the effectiveness of the proposed approach for real industrial cases. This research will combine both simulation-based method and optimization technique to improve the quality of solutions.

In AGV systems, the begin-end combinations are usually connected by using a fixed layout, which is not the optimal path. The capability of these configurations is limited and often the conflict of multiple AGVs and deadlock are inevitable. By appearing more flexible layouts and advanced technology, the positioning and dispatching of AGVs increased. A new concept would be to determine each path dynamically. This would use the free paths for AGVs leading to overcome the conflicts and deadlocks.

Business process workflow is a design conceptualization to automate the sequence of activities to achieve a business goal with involved participants and a predefined set of rules. Regarding this, a formal business workflow model is a prime requisite to implement a consistent and rigorous business process. In this context, majority of the existing research works are formalized structural features and have not focused on functional and behavioral design aspects of business processes. To address this problem, this paper aims to propose a formal model of business process workflow called as business process workflow using typed attributed graph (BPWATG) enriched with structural, functional and behavioral characteristics of business processes.

Typed attributed graph (ATG) and first-order logic have been used to formalize proposed BPWATG to provide rigorous syntax and semantics towards business process workflows. This is an effort to execute a business workflow on an automated machine. Further, the proposed BPWATG is illustrated using a case study to show the expressiveness of proposed model. Besides, the proposed graph is initially validated using generic modelling environment (GME) case tool. Moreover, a comparative study is performed with existing formal approaches based on several crucial features to exhibit the effectiveness of proposed BPWATG.

The proposed model is capable of facilitating structural, functional and behavioral aspects of business process workflows using several crucial features such as dependency conceptualization, timer concepts, exception handling and deadlock detection. These features are used to handle real-world problems and ensure the consistency and correctness of business workflows.

BPWATG is proposed to formalize a business workflow that is required to make a model of business process machine-readable. Besides, formalizations of dependency conceptualization, exception handling, deadlock detection and time-out concepts are specified. Moreover, several non-functional properties (reusability, scalability, flexibility, dynamicity, reliability and robustness) are supported by the proposed model.

To date, there has been little research about the degree of correspondence between partner equity ownership and partner representation on boards of joint ventures (JVs). It is generally assumed that partners’ share equals board representation in percentage. This paper aims to explore various instances of deviation from the above norm.

Using a unique database of 259 JV contracts extracted from the US Securities and Exchange Commission, and by drawing from resource dependency and transaction cost theories, this manuscript explores the factors that increase or decrease the deviation between equity share and board representation.

The results show that international JVs (IJVs) tend to deviate more, while JVs with a deadlock clause, a large board and based in a stable country deviate less from the degree of correspondence between equity share and board representation.

This study contributes to the alliance and governance literatures by identifying factors that influence the degree of correspondence between partner investment (equity share) and control through board of director representation.

The small area network for data communication within routers is suffering from storage of packet, throughput, latency and power consumption. There are a lot of solutions to increase speed of commutation and optimization of power consumption; one among them is Network-on-chip (NoC). In the literature, there are several NoCs which can reconfigurable dynamically and can easily test and validate the results on FPGA. But still, NoCs have limitations which are regarding chip area, reconfigurable time and throughput.

To address these limitations, this research proposes the dynamically buffered and bufferless reconfigurable NoC (DB2R NoC) using X-Y algorithm for routing, Torus for switching and Flexible Direction Order (FDOR) for direction finding between source and destination nodes. Thus, the 3 × 3 and 4 × 4 DB2R NoCs are made free from deadlock, low power and latency and high throughput. To prove the applicability and performance analysis of DB2R NoC for 3 × 3 and 4 × 4 routers on FPGA, the 22 bits for buffered and 19 bit for bufferless designs have been successfully synthesized using Verilog HDL and implemented on Artix-7 FPGA development bond. The virtual input/output chips cope pro tool has been incorporated in the design to verify and debug the complete design on Artix-7 FPGA.

In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.

In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.

Siphon-based deadlock control in a flexible manufacturing system (FMS) suffers from the problems of computational and structural complexity since the number of siphons grows exponentially with respect to the size of its Petri net model. In order to reduce structural complexity of a supervisor, a set of elementary siphons derived from all strict minimal siphons (SMS) is explicitly controlled. The purpose of this paper is through fully investigating the structure of a class of generalized Petri nets, WS3PR, to compute all SMS and a compact set of elementary siphons.

Based on graph theory, the concepts of initial resource weighted digraphs and restricted subgraphs are proposed. Moreover, the concept of augmented siphons is proposed to extend the application of elementary siphons theory for WS3PR. Consequently, the set of elementary siphons obtained by the proposed method is more compact and well suits for WS3PR.

In order to demonstrate the proposed method, an FMS example is presented. All SMS and elementary siphons can be derived from initial resource weighted digraphs. Compared with those obtained by the method in Li and Zhou, the presented method is more effective to design a structural simple liveness-enforcing supervisor for WS3PR.

This work presents an effective method of computing SMS and elementary siphons for WS3PR. Monitors are added for the elementary siphons only, and the controllability of every dependent siphon is ensured by properly supervising its elementary ones. A same set of elementary siphons can be admitted by different WS3PR with isomorphic structures.