Search results

The circuit elements of every printed circuit board have the potential for failure during test and/or use. These failures can occur by forming short‐circuits between adjacent circuit elements, or by forming open‐circuits in the conductors. The risk sites can be identified by type, and the total number enumerated by manual inspection of the photolithographic masks used to fabricate the printed circuit layers. However, the circuit density of high performance printed circuit boards has become so great that meaningful manual analysis has become impractical. A more effective method is to use special graphics programs to analyse the computer‐aided design (CAD) data. The methodology developed to perform the CAD analysis of high performance printed circuit boards for short‐circuits utilises two powerful computer graphic tools: the Interactive Graphics System and the Unified Shapes Checking system. Test data for open‐circuits are generated using specially written alphanumeric routines. The data can be used for stress testing the printed circuit boards by wiring up special test modules that are plugged into the boards and then placing the boards into environmental test chambers. The printed circuits are checked for short‐circuits by putting them into groups that have no risk of shorting to each other (zero risk), and placing the groups in parallel under an electrical potential. The flow of current between the groups would indicate a short‐circuit. Similarly, the printed circuits can be checked for open‐circuits, by stringing them together into groups in series, and measuring the changes in resistance under thermal stress. Both types of test data can also be used for in‐process testing.

Flex‐rigid circuits have been used for many years, primarily by the military, as a method to reduce the size and increase the reliability of electronic systems. However, in today's emerging designs where high speed ASICs are often the dominant components, flex‐rigid circuit assemblies are now an attractive solution for providing high density transmission line interconnects from board to board. Much of today's circuitry is being committed to ASIC designs to increase both circuit density and speed. Following this path, designers are faced with the task of interconnecting high lead count SMT packages often with as many as 300 to 500 leads per device, each dissipating several watts. At these power densities conductive cooling through the circuit board is often a necessity, dictating the use of either metal cores or heat exchangers. To make efficient use of the core and minimise weight, designs generally require SMT packages to be mounted on both sides of the core with electrical communication from side to side. However, as more exotic core materials (carbon fibre matrix, beryllium, etc.) and liquid cooled heat exchangers are used, electrical communication through the core has become difficult, if not impossible, in some cases. Instead, high density flex‐rigid assemblies are used to partition the circuit, allowing the board to ‘fold’ over the core. This results in hundreds of signal lines that must cross the flex, obeying the electrical design rules dictated by the rigid sections to maintain impedance values and crosstalk margins. This paper focuses on recent work at AIT, producing high density flex‐rigid circuits using embedded discrete wiring technology to meet the above requirements. Using 0.0025 in. diameter polyimide insulated wire, as many as 100 lines per linear inch can pass over the flex region on a single layer. This generally results in a single flex layer where all wires can be referenced to a continuous ground plane from board to board. Controlled impedance is easily maintained due to the uniform wire geometry, and high frequency attenuation is significantly lower than on equivalent etch circuit designs due to the smooth surface finish on the wire. In addition, the high interconnection density offered by this technique reduces the overall thickness of the rigid sections, thereby minimising the thermal resistance to the core.

In future generations, electronic systems will rely extensively on advanced IC technology to achieve higher performance levels. However, with limits placed on the level of integration that can be obtained on a single IC, a need still exists for an interconnection hierarchy to provide the necessary density transform between system components. A recent addition to many high performance interconnection structures has been the Multichip Module. By eliminating the conventional IC package, MCMs have dramatically reduced the electrical length between devices, thereby minimising propagation delay, crosstalk, and attenuation. Although MCM techniques will offer many performance advantages, they also present many design challenges at subsequent levels of interconnection. This paper will focus on the requirements of MCM backplanes interconnecting several modules and, as a solution, will present recent work on advanced metal core substrates. MCM substrates provide a tremendous density advantage, however, the interconnection between modules is still a formidable task. Modules often have I/O densities of 300 to 500 leads per square inch and typically dissipate 10 to 50 watts per square inch. In addition, with sub‐nanosecond rise times, the distance between modules is often sufficient for signal paths to be treated as transmission lines. In an effort to meet these requirements, metal core circuits based on copper, copper Invar, and copper molybdenum have been fabricated using 0·0025 in. diameter embedded discrete wiring technology. Combined with a Kevlar surface layer suitable for wire bonding and blind laser drilled vias to access the internal wires, this technique offers many benefits. As many as 4 conductors can pass between holes on 0·050 in. centres in a single wiring layer only 0·018 in. thick. With the absence of interstitial vias, additional substrate area can be dedicated to create a sizeable thermal path, essential to conduct the heat from the MCM to an internal metal core. Together, these features have made this an attractive approach for interconnecting multichip modules.

In the never‐ending quest for speed, designers are now turning to digital GaAs integrated circuits both to extend the bandwidth of current designs and in some cases to generate a whole new class of products never before possible. The engineer well versed in high speed ECL design techniques generally understands the problems associated with this transfer to GaAs logic. However, even with the design task well defined, the exact solution for interconnecting devices is often difficult and stresses the capabilities of existing multilayer printed circuit techniques using conventional dielectric materials and processing. This paper examines the design task in detail, and will present recent developments in shielded discrete wiring techniques as a possible solution for GaAs packaging.

Jointly determines the optimal level to which the mean of a critical variable should be set up, and the optimal number of repetitions until recalibration, for the case where the variable is distributed normally, the mean changes linearly with the number of repetitions, and the revenue per oversized and undersized item is unequal. Proves that the optimal set‐up level should be below the mid‐point between the specification limits by a distance which depends on the slope of change of the mean, on the recalibration cycle, and on a function of the per unit revenues, in such a manner that just prior to the recalibration the mean reaches a different distance above the mid‐point. Outlines a method for the numerical evaluation of the optimal number of cycle repetitions, and derives a general approximation formula which allows its closed loop determination. Provides a numerical example and sensitivity analysis.

Research on institutional logics has missed the opportunity to understand how and why societies may fundamentally differ in their material and symbolic systems. In this chapter, the authors offer a qualitative examination of the implementation of infrastructure public–private partnership (PPP) projects in the Arab state of Qatar. The authors illustrate how the macrofoundations of Qatari society are rooted in the notion of tribe, an inter-institutional system under which the intertwined institutional orders of the state, the market, and the family have historically developed and operated. Their study sheds light on how these macrofoundations shape the processes and mechanisms that underpin the resistance to the introduction of innovative organizational forms. The chapter makes two contributions. First, it identifies how “foreign” organizational forms rooted in Western institutional orders trigger adverse reactions from societies characterized by different institutional orders. Second, it demonstrates the challenge of implementing PPPs in an institutional context that is unfavorable to them and where actors seek to preserve the supremacy of the extant inter-institutional system.

Increasing speeds combined with the level of integration that can be obtained with advanced IC technology has dramatically changed the interconnection requirements for high performance electronic systems. With much of today's circuitry being implemented in custom silicon, IC technology has allowed both a dramatic reduction in size and a tremendous increase in performance. However, in terms of the interconnection problem, the by‐product of advanced IC technology is a new generation of IC s that often require several hundred I/OS, exhibit rise times of 150 ps to 300 ps, and dissipate several watts per device. As demanding requirements are placed upon circuit boards, the complexity of the design task increases dramatically, since a working solution must simultaneously address interconnection density, signal integrity and thermal performance. This paper examines embedded discrete wiring technology as a high density solution that meets the requirements necessary for transporting high speed digital signals.

Plant relocation (PR) is a major organisational change, ostensibly focused only upon geographical transfer, but in fact having broad‐spectrum accompanying effects. A conceptual analysis of PR is presented, supplemented by data from 35 interviews with managers and union leaders of organisations having recently relocated. PR is viewed as a catalytic process of turbulent change, radiating upon organisational structures, social processes, and external environmental systems. The uncertainty and turbulence created by PR are shown to affect management‐worker relations, as well as the interrelationships among employees and the distribution of power within the organisation. The potentials of PR as an opportunity for organisational growth and revitalisation on the one hand, and as a period of crisis and turmoil, on the other, are presented. Some general guidelines are proposed for the effective planning and management of relocation.

The purpose of this paper is to establish that there are causal relationships among critical success factors (CSFs) associated with an enterprise resource planning (ERP) project. The authors prove that: H1 – Vendor (VN) is positively related to Enterprise System Selection Process (ES). H1a – Enterprise System Selection process (ES) mediates the relationship between vendor (VN) and Success (SS). H2 – Project Management (PM) is positively related to Implementation Strategy (IS). H2a – Implementation Strategy (IS) mediates the relationship between Project Management (PM) and Success (SS). H3 – Support of Top Management (TM) is positively related to Project Team Competence (PT). H3a – Project Team Competence (PT) mediates the relationship between Support of Top Management (TM) and Success (SS).

To test the proposed hypotheses, the authors conducted a survey using a questionnaire. The research questionnaire was floated to 450 respondents; the authors received 168 responses. The authors had to discard 62 responses as their organization had greater than 250 employee and did not qualify to be an Indian SME. The authors were left with 106 responses. The respondents were managers (5.6 percent), consultants (39.6 percent), engineers (50 percent) and the remaining (4.8 percent) did not specify their job. The authors then do regression analysis and path analysis including all other required analysis.

The authors found that all hypotheses are supported. The management may use these findings to understand relationships among CSFs and use this knowledge to mitigate and manage CSFs.

There are no systematic studies to study relationships among CSFs. The work establishes relationships among CSFs through data collected from organizations that have implemented ERP.

Centralization, which indicates distribution of decision-making power in organizations, is well-discussed in innovation literature as one of the influencing factors of innovation implementation. Motivated by a gap in enterprise resource planning (ERP) research, the purpose of this paper is to investigate the influence of centralization on the success of ERP implementation.

Centralization is characterized twofold: policy-related centralization (PRC) and work-related centralization (WRC). ERP implementation success is captured in terms of user acceptance and the use of the ERP system. Using organizational innovation theory, six hypotheses relating centralization, ERP implementation success, and organization size are built and tested using data gathered from 51 Indian organizations that implemented ERP. The data are analyzed using partial least squares-structural equation modeling.

User acceptance is significantly inhibited by PRC. WRC has a negative influence on use. The negative influence of PRC on acceptance is more pronounced in the case of larger organizations. On the whole, a decentralized set-up is favorable to ERP implementation success.

The study highlights the impact of a centralized management structure on success of ERP implementation and in doing so, it demarcates the varied influence of two types of centralization. It contributes to the scarce research on ERP implementation using the strong theoretical basis of organizational innovation. The findings highlight the implications of centralization to the implementation outcomes, for organizations embarking upon ERP.