In future generations, electronic systems will rely extensively on advanced IC technology to achieve higher performance levels. However, with limits placed on the level of integration that can be obtained on a single IC, a need still exists for an interconnection hierarchy to provide the necessary density transform between system components. A recent addition to many high performance interconnection structures has been the Multichip Module. By eliminating the conventional IC package, MCMs have dramatically reduced the electrical length between devices, thereby minimising propagation delay, crosstalk, and attenuation. Although MCM techniques will offer many performance advantages, they also present many design challenges at subsequent levels of interconnection. This paper will focus on the requirements of MCM backplanes interconnecting several modules and, as a solution, will present recent work on advanced metal core substrates. MCM substrates provide a tremendous density advantage, however, the interconnection between modules is still a formidable task. Modules often have I/O densities of 300 to 500 leads per square inch and typically dissipate 10 to 50 watts per square inch. In addition, with sub‐nanosecond rise times, the distance between modules is often sufficient for signal paths to be treated as transmission lines. In an effort to meet these requirements, metal core circuits based on copper, copper Invar, and copper molybdenum have been fabricated using 0·0025 in. diameter embedded discrete wiring technology. Combined with a Kevlar surface layer suitable for wire bonding and blind laser drilled vias to access the internal wires, this technique offers many benefits. As many as 4 conductors can pass between holes on 0·050 in. centres in a single wiring layer only 0·018 in. thick. With the absence of interstitial vias, additional substrate area can be dedicated to create a sizeable thermal path, essential to conduct the heat from the MCM to an internal metal core. Together, these features have made this an attractive approach for interconnecting multichip modules.
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