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The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients.

The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches.

In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents.

The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.

Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process.

Initially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved.

The designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW.

A time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC.

The designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society.

The implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power.

This paper presents a prediction on the impact of technology scaling on phase‐locked loop (PLL) performance behaviour. Power and maximum operating frequency of an Analogue PLL and a Type II phase‐frequency detector (PFD)‐based PLL from which the behaviours of other PLLs derived from the two architectures can be estimated, are analysed and their future behaviours as a function of technology are predicted.

Analogue models were developed and Mentor Graphics VHDL‐AMS mixed‐signal simulations were performed on the two PLL architectures. Behavioural power and frequency equations as a function of technology were derived based on thorough data and graphical analyses.

A prediction of PLL frequency and power dissipation as a function of technology for two main PLL architectures.

The parameters in each equation derived should include other contributing factors as well as other design approaches such as multi‐VDD, multi‐Vth, etc. future work should also include prediction of jitter and phase noise for the two main PLL topologies.

This paper is of high significance in PLL design. The predicted equations could be used to reduce a major portion of a PLL designers' design time when choosing a PLL topology, and help them predict the impact of technology on the performance of the chosen architecture.

The linear analysis presented for the charge pump phase locked loops (CPPLLs) becomes inaccurate or incorrect where cycle slipping occurs. In this paper, an analytical approach is proposed, which explains the conditions in which cycle slipping happens. Using the analytical results, one can simply design or redesign a CPPLL to prevent or decrease cycle slipping and hence decreasing the locking time. The paper aims to discuss these issues.

To obtain cycle slipping conditions, CPPLL's signals in the time domain are tracked and cycle slipping condition is investigated. Based on the proposed analysis, by comparing a simple function of system's parameters with a threshold, cycle slipping is predicted.

The cycle slipping conditions are expressed in terms of system's parameters and the size of the input frequency step. The method is also generalized for a fast CPPLL with an aid-lock BBFC circuit. The good accuracy of the analytical predictions is verified using simulations in Matlab/Simulink.

A new analytical method for cycle slipping prediction in CPPLLs is presented. A closed form equation in terms of system's parameters and input frequency step has been presented, which can predict the cycle slipping possibility in the system without a need to perform the full time-consuming simulations. This analytical method that uses the LambertW function's properties proposes a threshold to predict cycle slipping in the system. This method not only can be used by designers to predict cycle slipping but can also be used to design the CPPLL in order to remove or decrease cycle slipping. The method is also generalized for fast locking charge pump PLLs and as a case study, cycle slipping prediction in the BBFC-CPPLL is performed.

Charge pump phase locked loops (CPPLLs) are nonlinear systems as a result of the nonlinear behavior of voltage-controlled oscillators (VCO). This paper aims to specify jitter generation of voltage controlled oscillator phase noise in CPPLLs, by considering approximated practical model for VCO.

CPPLL, in practice, shows nonlinear behavior, and usually in LC-VCOs, it follows second-degree polynomial function behavior. Therefore, the nonlinear differential equation of the system is obtained which shows the CPPLLs are a nonlinear system with memory, and that Volterra series expansion is useful for such systems.

In this paper, by considering approximated practical model for VCO, jitter generation of voltage controlled oscillator phase noise in CPPLLs is specified. Behavioral simulation is used to validate the analytical results. The results show a suitable agreement between analytical equations and simulation results.

The proposed method in this paper has two advantages over the conventional design and analysis methods. First, in contrast to an ideal CPPLL, in which the characteristic of the VCO’s output frequency based on the control voltage is linear, in the present paper, a nonlinear behavior was considered for this characteristic in accordance with the real situations. Besides, regarding the simulations in this paper, a behavior similar to the second-degree polynomial was considered, which caused the dependence of the produced jitter’s characteristic corner frequency on the jitter’s amplitude. Second, some new nonlinear differential equations were proposed for the system, which ensured the calculation of the produced jitter of the VCO phase noise in CPPLLs. The presented method is general enough to be used for designing the CPPLL.