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The linear analysis presented for the charge pump phase locked loops (CPPLLs) becomes inaccurate or incorrect where cycle slipping occurs. In this paper, an analytical approach is proposed, which explains the conditions in which cycle slipping happens. Using the analytical results, one can simply design or redesign a CPPLL to prevent or decrease cycle slipping and hence decreasing the locking time. The paper aims to discuss these issues.

To obtain cycle slipping conditions, CPPLL's signals in the time domain are tracked and cycle slipping condition is investigated. Based on the proposed analysis, by comparing a simple function of system's parameters with a threshold, cycle slipping is predicted.

The cycle slipping conditions are expressed in terms of system's parameters and the size of the input frequency step. The method is also generalized for a fast CPPLL with an aid-lock BBFC circuit. The good accuracy of the analytical predictions is verified using simulations in Matlab/Simulink.

A new analytical method for cycle slipping prediction in CPPLLs is presented. A closed form equation in terms of system's parameters and input frequency step has been presented, which can predict the cycle slipping possibility in the system without a need to perform the full time-consuming simulations. This analytical method that uses the LambertW function's properties proposes a threshold to predict cycle slipping in the system. This method not only can be used by designers to predict cycle slipping but can also be used to design the CPPLL in order to remove or decrease cycle slipping. The method is also generalized for fast locking charge pump PLLs and as a case study, cycle slipping prediction in the BBFC-CPPLL is performed.

Charge pump phase locked loops (CPPLLs) are nonlinear systems as a result of the nonlinear behavior of voltage-controlled oscillators (VCO). This paper aims to specify jitter generation of voltage controlled oscillator phase noise in CPPLLs, by considering approximated practical model for VCO.

CPPLL, in practice, shows nonlinear behavior, and usually in LC-VCOs, it follows second-degree polynomial function behavior. Therefore, the nonlinear differential equation of the system is obtained which shows the CPPLLs are a nonlinear system with memory, and that Volterra series expansion is useful for such systems.

In this paper, by considering approximated practical model for VCO, jitter generation of voltage controlled oscillator phase noise in CPPLLs is specified. Behavioral simulation is used to validate the analytical results. The results show a suitable agreement between analytical equations and simulation results.

The proposed method in this paper has two advantages over the conventional design and analysis methods. First, in contrast to an ideal CPPLL, in which the characteristic of the VCO’s output frequency based on the control voltage is linear, in the present paper, a nonlinear behavior was considered for this characteristic in accordance with the real situations. Besides, regarding the simulations in this paper, a behavior similar to the second-degree polynomial was considered, which caused the dependence of the produced jitter’s characteristic corner frequency on the jitter’s amplitude. Second, some new nonlinear differential equations were proposed for the system, which ensured the calculation of the produced jitter of the VCO phase noise in CPPLLs. The presented method is general enough to be used for designing the CPPLL.