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No‐clean flux printed board appraisal tests were conducted with all materials used in the production process. Metallic growths during environmental testing revealed that there was incompatibility between some materials used. Initial tests with two solder resists and several fluxes showed that one non solder resisted board, soldered using a synthetically activated (SA) flux, had surface insulation resistance (SIR) two decades higher than those using low solids flux (LSF) or other SAs. For boards with solder resist, the SIR of those soldered using LSFs was higher, however, than those using SA fluxes. SIR dependence on temperature and humidity was investigated. Results demonstrated that the dominant factor to determine the SIR of a no‐clean board was the characteristics of the board substrate finish. SIR changes with condensation were logged and found to be significant for solder resist finishes. Tests proved that reducing the contamination levels under and on top of the solder resist, by using hot de‐ionised water rinsing, enabled the calculated minimum SIR level to be achieved for spray fluxed boards and minimised the possibility of metallic growth. Visual examination proved to be at least as important as SIR testing. No‐clean processes were appraised using sequential environmental conditions with differing SIR pass levels. As a result of this appraisal a maximum ionic contamination level of 0·5 μg/cm2 NaCl equivalent and Dl water rinses, before and after solder resist added, will be introduced. Ionic contamination tests indicated that contamination levels reduced with elapsed time, probably due to ionic molecules locking more firmly into the board surface structure. A novel method for SIR measurements at any voltage, developed by the author, is described. It is hoped that this paper will further the understanding of no‐clean flux issues and highlight potential solutions and pitfalls.

Modern electronics is characterised by the increasing level of integration in printed circuit board (PCB) technology and the reduced insulation spacing between adjacent conductors. Surface insulation resistance (SIR) measurement has often been used alone to determine the cleanliness of PCB assembly; however, when proper SIR measurement is used in conjunction with surface leakage current (SLC) measurement, the result can reveal the dynamic nature of surface electrochemical migration (SECM) processes at the microscopic level, and the effect of such processes on product quality and reliability. This paper presents a newly developed measurement methodology, which measures SLC per square unit area at a sampling rate that is orders of magnitude higher than that of conventional SIR measurement methods. It is aimed to capture the transient surge of SLC which is detrimental to the functionality of product.

The need to use cleaning methods other than traditional CFC‐113 solvent for hi‐rel electronics imposes more rigid cleanliness testing. In the past, this was mainly limited to ionic contamination control, but this is probably insufficient by itself when using other methods. This paper discusses the various methods for which instrumentation is available, from the practical standpoint. This should satisfy all the requirements of both procurement agencies and manufacturers. Particular emphasis is placed on the fact that most existing standards are out‐of‐date and should be urgently revised. It is suggested that the standards be based on statistically valid test results rather than the simpler, but risky, go/no‐go methods. These probability limit levels should be modulated according to the use to which the circuitry will be put and the technology used in its manufacture. Above all, emphasis is placed on testing methods that are more scientifically based with less empirical guesswork.

The transition to surface mounted device (SMD) technology in electronics manufacturing has placed new demands on the post‐solder cleaning process. For spacecraft electronic systems it is of the utmost importance that all flux residues be removed. This paper reports the results of an investigation of the impact of component stand‐off heights and the distance between solder joints on the cleaning process efficiency. The capability to clean beneath large chip carriers was evaluated for four different cleaning methods using isopropanol or CFC‐113 (Freon TMS) as cleaning liquid. The results show that the cleaning efficiency decreases considerably if the stand‐off height is less than 240 µm for 100 mil pitch chip carriers. For 50 mil pitch chip carriers the stand‐off height needs to be greater than 240 µm to achieve high cleaning efficiency. The cleaning efficiency beneath chip carriers with small stand‐off heights can be increased by using ultrasonic cleaning. However, a very thin layer of white residues is left where the flux has been removed if isopropanol is used as the cleaning liquid.

This paper aims to discuss the effects of ionic contaminations on the die surface of high lead flip chip ball grid array (FCBGA) package. Ionic contaminations from the flux residue, formed during the die attachment process, could affect the package long‐term performance.

Thus, the flux‐cleaning process was implemented and the cleanliness effect was evaluated. Cleaning experiments using a new water‐based solvent were carried out to investigate the flux‐cleaning efficiency. The test packages were then evaluated via ion chromatography (IC).

Ion chromatograms show that there are high levels of ionic elements detected prior to the cleaning process. After the cleaning process, the contamination levels reduced significantly.

The value of the work here is testing of the new environmental friendly water‐based MPC^® cleaning efficiency. The reduction of ionic contamination is thus reported.

The efficiency of cleaning of flux residues after various periods of ageing was assessed by measuring the ionic contamination removed in an Ionograph 500 SMD. The flux residues were removed from bare boards, and boards with through hole and surface mount components. The effect of different ageing temperature was also investigated. The work has shown that there is a maximum time interval following assembly during which cleaning should be carried out. The ionic contamination of aged assemblies with through hole and surface mount components were cleaned with varying efficiencies. The surface mount components were more difficult to clean. The use of brushing and scrubbing proved particularly beneficial for the through hole components. A proprietary cleaner proved more effective than the generic alternatives considered.

The contamination on SMT assemblies caused by a number of flux/cleaning variation has been investigated, with several analysis methods used to quantify the contamination. The results from analysis of test printed circuit boards (PCBs) using anion separation, conductivity, ionic contamination measurement, visual and SEM inspection, microsections and surface insulation resistance (SIR) methods were compared. The best cleaning result was observed with the combination of water soluble (WS) solder cream and water cleaning. The best measurement method for cleanliness of PCBs was considered to be SIR measurement. For WS fluxes, the iconic contamination test offers effective measurement of the amount of residues left on the PCBs.

In view of the uncertainty of the applicability of traditional ionic contamination measurement to surface mount assemblies, a mathematical study was made of the phenomena involved. A model was derived, showing that under‐component contamination behaves differently from ordinary surface contamination. By breaking down a curve obtained under practical conditions into its components, it is therefore possible to derive separate figures for surface and under‐component ionic contamination, ignoring the influence of spurious noise signals. A new software, using these techniques, has been written for this application. Comparative tests between non‐destructive testing, using this software, and tests on similar circuits with the components torn off, show that there is a close correlation between the results from these two techniques, even though the under‐component contamination is only partially dissolved with the former method.

The purpose of this paper is to evaluate and compare the effectiveness and sensitivity of different cleanliness verification tests for post soldered printed circuit board assemblies (PCBAs) to provide an understanding of current industry practice for ionic contamination detection limits.

PCBAs were subjected to different flux residue cleaning dwell times and cleanliness levels were verified with resistivity of solvent extract, critical cleanliness control (C3) test, and ion chromatography analyses to provide results capable of differentiating different sensitivity levels for each test.

This study provides an understanding of current industry practice for ionic contamination detection using verification tests with different detection sensitivity levels. Some of the available cleanliness monitoring systems, particularly at critical areas of circuitry that are prone to product failure and residue entrapment, may have been overlooked.

Only Sn/Pb, clean type flux residue was evaluated. Thus, the current study was not an all encompassing project that is representative of other chemistry‐based flux residues.

The paper provides a reference that can be used to determine the most suitable and effective verification test for the detection of ionic contamination on PCBAs.

Flux residue‐related problems have long existed in the industry. The findings presented in this paper give a basic understanding to PCBA manufacturers when they are trying to choose the most suitable and effective verification test for the detection of ionic contamination on their products. Hence, the negative impact of flux residue on the respective product's long‐term reliability and performance can be minimized and monitored effectively.