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The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM).

Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ.

It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit.

This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay.

The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node.

This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out.

The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.

The purpose of this paper is to explore and evaluate the performance comparison of carbon nanotubes (CNT) and nickel silicide (NiSi) nanowires interconnects as prospective alternatives to copper wire interconnects.

The increasing resistivity of the copper wire with scaling and rising demands on current density drives the need for identifying new wiring solutions. This paper explores the various alternatives to copper. The metallic bundle CNTs and NiSi nanowires are promising candidates that can potentially address the challenges faced by copper. This paper analyzes various electrical models of carbon nanotube and recently introduced novel interconnect solution using NiSi nanowires.

The theoretical studies proves CNTs and NiSi nanowires to be better alternatives against copper on the ground of performance parameters, such as effective current density, delay and power consumption. NiSi nanowire provides highest propagation speed for short wire length, and copper is the best for intermediate wire length, while bundle CNTs is faster for long wire length. NiSi nanowire has lowest power consumption than copper and CNTs.

This paper investigates, assess and compares the performance of carbon nanotubes (CNT) and NiSi nanowires interconnects as prospective alternatives to copper wire interconnects in future VLSI chips.

The purpose of this paper is to analyze the effect of driver size and number of shells on propagation delay and power for multi‐walled carbon nanotubes (MWCNT) interconnects at 22 nm technology node.

An equivalent circuit model of MWCNT is used for estimation and analysis of propagation delay and power. The delay and power through MWCNT and Cu interconnects are compared for various driver sizes and number of MWCNT shells.

The SPICE simulation results show that the MWCNT interconnect has lower propagation delay than Cu interconnects. The delay ratio of MWCNT to Cu decreases with increase in length for different driver size and number of MWCNT shells. However, the delay ratio increases with reduction in number of MWCNT shells. The ratio of average power consumption (MWCNT/Cu) also decreases with the variation in driver size and numbers of shells with respect to the length of interconnect. The theoretical study proves CNTs to be better alternatives against copper on the ground of performance parameters.

Several challenges remain to be overcome in the areas of fabrication and process integration for CNTs. Lowering of metal nanotube contact resistance would be vital, especially for local interconnect and via applications. Moreover, rigorous characterization and modeling of electromagnetic interactions in CNT bundles; 3‐D (metal) to 1‐D (CNT) contact resistance; impact of defects on electrical and thermal properties; and high‐frequency effects are being seen as additional challenges.

This paper investigates, assesses and compares the performance of carbon nanotubes (CNT) based interconnects as prospective alternatives to copper wire interconnects in future VLSI chips. Multi walled CNTs assure for long/global interconnect applications.

The purpose of this paper is to propose an analytical model for estimating propagation delay in coupled resistance-inductance-capacitance (RLC) interconnects.

With higher frequency of operation, longer length of interconnect and fast transition time of the signal, the resistor capacitor (RC) models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are required. In this paper, an analytical model for estimation of interconnect delay is developed for simultaneously switching lines. Two distributed RLC lines coupled inductively and capacitively are considered. To validate the proposed model, SPICE results are compared with the proposed analytical results. Each line in the coupled structure is terminated by a capacitive load of 30fF. The driving signal is considered symmetrical with equal rise and fall time of 5 ps and OFF/ON time of 45 ps. The model is validated for both in-phase and out of phase switching of lines.

It is observed that the model works well for both the phases of inputs switching. The derived expressions of delay exhibit complete physical insight, and the results obtained are in excellent agreement with SPICE results. Comparison of analytical delay with SPICE delay shows an average error of < 2.7 per cent.

The analytical expressions for interconnect delay are derived for the first time under simultaneously switching scenario. This model is useful to estimate delay across the inductively and capacitively coupled interconnects.

This paper proposes to study the effect of line resistance and driver width on crosstalk noise for a CMOS gate driven inductively and capacitively coupled VLSI interconnects.

The paper considers a distributed RLC interconnect topology. The interconnect length is 4 mm and far‐end capacitive loading is 30 fF. The SPICE simulation set‐up uses an IBM 0.13 μm, 1.2 V technology model. The input falling ramp has a transition time of 50 ps. The victim line is grounded through a driver resistance of 50 Ω at near end of interconnect. While observing the effect of line resistance, the aggressor driver has PMOS and NMOS widths of 70 and 30 μm, respectively, and the line resistance is varied from 0 to 500 Ω. For capturing the effect of driver width, SPICE waveforms are generated at far end of victim line for three different line resistances (R=0, 30, and 60 Ω respectively). In each case, the aggressor PMOS driver width is swept from 20 to 100 μm. The corresponding NMOS width is half of PMOS width.

It is observed that, as line resistance increases, the noise peak reduces. This is due to the fact that with increasing resistance the incident and reflected waves traveling along the line experience increasing attenuation. Hence, the waves arriving at the far‐end of the line are of smaller magnitude and larger time durations. This causes noise pulses in the lossy lines to be smaller and wider compared with those in a lossless line. The effect of driver width on noise waveforms is further observed. It is observed that, as the PMOS (and corresponding NMOS) driver width is increased, the victim line gets more prone to crosstalk noise. The crosstalk magnitude level increases alarmingly as driver width is increased, because the driver resistance decreases, which in turn increases the current driving capability of driver.

While designing coupled interconnects, driver width and line resistance play an important role in deciding the crosstalk level. An interconnect designer often increases driver width and reduces line resistance for achieving lower propagation delays. This effort may result in higher crosstalk noise in coupled interconnect. Therefore, a designer should be concerned simultaneously for crosstalk noise while reducing delays.

To analyze factors affecting crosstalk and to study the effect of repeater insertion on crosstalk, power dissipation and propagation delay.

Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13 μm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. Further, to study the effect of repeater insertion on crosstalk, repeaters are inserted in one line, i.e. line A only. Uniform repeaters varying in number from 1 to 60 are each of size W_n=3.9 μm and W_p=7.8 μm. Both lines A and B are terminated by a capacitive load of 5 fF. A crosstalk noise effect is measured for line A loaded with repeaters. The number of repeater is varied for four different cases of stimulations to both lines viz. input to line A, i.e. V_A switching from low to high; input to line B, i.e. V_B switching from low to high; input to line A i.e V_A switching from low to high; input to line B, i.e. V_B switching from high to low; V_A switching from high to low and V_B at static low; V_A switching from high to low and V_B at static high.

This paper shows the prominent factors such as edge rate, length and pattern of inputs affecting the noise. It is observed that presence of inductive effects can seriously hamper the functioning of the chip. This paper further reveals that repeater insertion not only reduces the propagation delay but also crosstalk levels for coupled lines. Repeaters can be efficiently utilized for reduction of propagation delay and crosstalk noise at a trade of marginal increase in power dissipation. The power‐delay‐crosstalk‐product (PDCP) criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Based on PDCP a reduction in crosstalk of about 60 times and delay of 4.2 percent is achieved at trade of 13.2 percent increase in power dissipation in comparison to PDP.

The PDCP criterion is introduced as an efficient technique to insert repeater in coupled interconnects. Instead of PDP criterion, PDCP criterion is best suited for determination of optimum number of repeaters for overall minimization of delay, power and crosstalk.

The performance of a high‐speed chip is highly dependent on the interconnects, which connect different macro cells within a VLSI chip. Delay, power dissipation and cross‐talk are the major design constraints for high performance VLSI interconnects. The importance of on‐chip inductance is continuously increasing with higher clock frequency, faster on‐chip rise time, wider wires, ever‐growing length of interconnects and introduction of new materials for low resistance interconnects. In the current scenario, interconnect is modeled as an RLC transmission line. Interconnect width optimization plays an important role in deciding transition delay and power dissipation. This paper aims to optimize interconnect width for a matched condition to reduce power and delay parameters.

Width optimization is done for two sets of interconnect terminating conditions, namely active gate and passive capacitance. SPICE simulations have been used to validate the findings.

For a driver interconnect load model terminated by an active gate load, a trade‐off exists between short circuit and dynamic power in inductive interconnects, since with wider lines dynamic power increases, but short circuit power of the load gate decreases due to reduced transient delay. Whereas, for a line terminated by a capacitor, such trade‐off does not exist. Many of the previous researches have modeled the active gate load at the terminating end by its input parasitic gate capacitance.

This paper shows that such modeling leads to inaccuracy in estimation of power, and therefore non‐optimal width selection, especially for large fan‐out conditions.

The finding is that the impedance matching between transmission line at driver and load ends plays an important role in estimation of overall power dissipation and transition delay of a VLSI circuit.

To review and explore optical fiber and carbon nanotube (CNT) as prospective alternatives to copper in VLSI interconnections.

As the technology moves to deep submicron level, the interconnect width also scales down. Increasing resistivity of copper with scaling and rising demands on current density drives the need for identifying new wiring solutions. This paper explores various alternatives to copper. Metallic CNTs, optical interconnects are promising candidates that can potentially address the challenges faced by copper.

Although, the theoretical aspects proves CNTs and optical interconnect to be better alternative against copper on the ground of performance parameters such as power dissipation, switching delay, crosstalk. But copper would last for coming decades on integration basis.

This paper reviews the state‐of‐the‐art in CNT interconnect and optical interconnect research; and discusses both the advantages and challenges of these emerging technologies.