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Privacy and security of personal data is the prime concern in any communication. Security algorithms play a crucial role in privacy preserving and are used extensively. Therefore, these algorithms need to be effective as well as energy-efficient. Advanced Encryption Standards (AES) is one of the efficient security algorithms. The principal purpose of this research is to design Energy efficient implementation of AES, as it is one of the important aspects for a step toward green computing.

This paper presents a low voltage complementary metal oxide semiconductor (LVCMOS) based energy efficient architecture for AES encryption algorithm on Field Programmable Gate Array (FPGA) platform. The experiments are performed for five different FPGAs at different input/output standards of LVCMOS. Experiments are performed separately at two frequencies (default and 1.6 GHz).

The comparative study of total on-chip power consumption for different frequency suggested that LVCMOS12 performed best for all the FPGAs. Also, Kintex-7 Low Voltage was found to be the best performing FPGA. At 1.6 GHz frequency, the authors observed 55% less on-chip power consumption when switched from Artix-7 with LVCMOS33 (maximum power consuming combination) to Kintex-7 Low Voltage with LVCMOS12. Mathematical models are developed for the proposed design.

The green implementation of AES algorithm based on LVCMOS standards has not been explored yet by researchers. The energy efficient implementation of AES will certainly be beneficial for society as it will consume less power and dissipate lesser heat to environment.

The Purpose of this research is to make an energy efficient finite state machine (FSM) in order to achieve the core objective of green computing because FSM is an indispensable part of multiple computer hardware.

This study uses ultra-scale plus FPGA architecture in place of seven-series field-programmable gate array (FPGA) for the implementation of the FSM design and also uses output load scaling for the design of environment-friendly FSM. This design study is done using Verilog Hardware description language and Vivado integrated system environment design tools and implemented on 16 nm ultra-scale FPGA architecture.

There is up to 98.57% reduction in dynamic power when operating frequency is managed as per smart job scheduling. There is up to a 21.97% reduction in static power with proper management of output load capacitance. There is up to 98.43% saving in dynamic power with the proposed management of output load capacitance.

The proposed design will be environment friendly that eventually leads to the green earth. This is the main motive of the research area i.e. green computing.

This paper aims to characterize the sexual maturation of M. flexuosa plantations in Tulumayo.

The methodology in this paper was selection of three plots in open field and usage of different densities of planting, after the maturation of the first plants, we began the quarterly evaluation. There was total 28 evaluations in seven years of age.

As a result, it was determined that at 12 years, the plots with lower density presented a greater number of mature individuals, with a predominance of female palms that produced an average of four bunches of fruit per year, and males five inflorescences. In addition, 15% of adult female plants went dormant, whereas males accounted for 3.4%. Reproductive cycles began in September and culminated in October of the following year, which were synchronized with rainfall.

Planting density was a determining factor in the early maturity of M. flexuosa and sustainable plantation management.