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Article
Publication date: 7 February 2022

Yavar Safaei Mehrabani, Mojtaba Maleknejad, Danial Rostami and HamidReza Uoosefian

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and…

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Abstract

Purpose

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.

Design/methodology/approach

Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.

Findings

Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.

Originality/value

The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

Details

Circuit World, vol. 49 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 21 August 2019

Yavar Safaei Mehrabani, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi and Abolghasem Ghasempour

This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs).

Abstract

Purpose

This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs).

Design/methodology/approach

To design this cell, the capacitive threshold logic (CTL) has been used.

Findings

To evaluate the proposed cell, comprehensive simulations are carried out at two levels of the circuit and image processing. At the circuit level, the HSPICE software has been used and the power consumption, delay, and power-delay product are calculated. Also, the power-delaytransistor count product (PDAP) is used to make a compromise between all metrics. On the other hand, the Monte Carlo analysis has been used to scrutinize the robustness of the proposed cell against the variations in the manufacturing process. The results of simulations at this level of abstraction indicate the superiority of the proposed cell to other circuits. At the application level, the MATLAB software is also used to evaluate the peak signal-to-noise ratio (PSNR) figure of merit. At this level, the two primary images are multiplied by a multiplier circuit consisting of 4:2 compressors. The results of this simulation also show the superiority of the proposed cell to others.

Originality/value

This cell significantly reduces the number of transistors and only consists of NOT gates.

Details

Circuit World, vol. 45 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

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