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WEAR resistance is never the sole requirement of an engineering material. All engineering components have a function to perform and any particular function will impose a series of requirements on the material of manufacture. In the search for improved wear resistance, these other requirements must never be forgotten: no industrially useful material will survive on wear resistance alone.

Path generation is an important factor that affects the quality and efficiency of most laminated manufacturing processes such as SLS, SLA and FDM. This paper introduces an efficient path generation algorithm. The principle of the algorithm and its implementation are presented. A comparative study is used to analyze the effectiveness of this method. The results of comparison on both path length and processing time between the traditional method and the proposed method are discussed.

Interlaminar short circuits in turbo generator stators can lead to local damage of the iron core. The purpose of this paper is to model an interlaminar short circuit diagnosis test on an existing structure.

This work presents the modeling of short‐circuited laminations in a stator yoke of a turbo‐generator. A 3D finite element model, associated to a homogenization technique, is used to calculate the short‐circuit current. The diagnosis test known as El Cid has been modelled as well.

Calculation results are compared with the experiment. The same tendency has been observed both in experimental and numerical results.

Additional calculations may be performed (parametric studies) in order to investigate El Cid measuring under different conditions (different material properties, fault position, size), which may lead to a better interpretation of the results.

Modelling of short circuit diagnosis tests under different conditions may help with the interpretation of measuring results, predicting the fault size/seriousness and location. So, only the concerned parts of the stator have to be disassembled and repaired/rebuilt.

It is not easy to model numerically a structure with a short circuit inside, since different dimensions are involved: the fault and the varnish between laminations are much smaller than the stator itself. Thus, homogenization techniques have been used to model the lamination stack region. The combination of this technique with the modelling of the El Cid test constitutes a tool to study this kind of fault and calculate its severity and location in a stator.

Observation by optical microscopy and EBSP have made it clear that the trigger for the grain coarsening phenomenon of austenite stainless steel BS304S31 may be the stacking faults concentrating selectively in a thin layer lying just beneath the grain boundary. When macroscopic plastic strain reached 6 percent, selective concentration of stacking faults was observed. When it reached 20 percent, the distribution of stacking faults became uniform in each grain. After these specimens were heated, concentration of stacking faults disappeared, and grain coarsening occurred at the point with 6 percent strain, but no grain coarsening occurred at the point with 20 percent strain. In order to investigate this concentration of stacking faults, an attempt was made to analyze the deformation in each crystal by using image‐based FEM. The result suggested that there is a possibility that plastic strain concentrates in the vicinity of the grain boundary when the macroscopic plastic strain is small.

This paper aims to present a new fault detection and classification scheme of both DC faults and AC faults on a DC microgrid network.

To achieve reliable protection, the derivative of DC current signal is decomposed into several intrinsic modes using variational mode decomposition (VMD), which are then used as inputs to the Hilbert–Haung transform technique to obtain the instantaneous amplitude and frequency of the decomposed modes of the signal. A weighted Kurtosis index is used to obtain the most sensitive mode, which is used to compute sudden change in discrete Teager energy (DTE), indicating the occurrence of the fault. A stacked autoencoder-based neural network is applied for classifying the pole to ground (PG), pole to pole (PP), line to ground (LG), line to line (LL) and three-phase line to ground (LLLG) faults. The effectiveness of the proposed protection technique is validated in MATLAB/SIMULINK by considering different test cases.

As the maximum fault detection time is only 5 ms, the proposed detection technique is very fast. A stacked autoencoder-based neural network is applied for classifying the PG, PP, LG, LL and LLLG faults with classification accuracy of 99.1%.

The proposed technique provides a very fast, reliable and accurate protection scheme for DC microgrid system.

After reviewing a previous work on the disappearance of a stacking fault in the hard-sphere (HS) system confined between the top and bottom flat walls under gravity, we present results of a Monte Carlo (MC) simulation of HSs confined between the top flat wall and the bottom square patterned wall under gravity. In MC simulations of HSs between flat walls we observed disappearance of an intrinsic stacking fault through the glide of the Shockley partial dislocation in fcc (001) stacking forced by the stress from a small simulation box. The artifact that the driving force for the fcc (001) growth was the stress from the simulation box has been circumvented; the stress realizing the fcc (001) stacking has been replaced by that from square pattern on the bottom wall. Defect disappearance has also been observed for the square patterned bottom wall case.

The purpose of this paper is to propose a approach for data visualization and industrial process monitoring.

A deep enhanced t-distributed stochastic neighbor embedding (DESNE) neural network is proposed for data visualization and process monitoring. The DESNE is composed of two deep neural networks: stacked variant auto-encoder (SVAE) and a deep label-guided t-stochastic neighbor embedding (DLSNE) neural network. In the DESNE network, SVAE extracts informative features of the raw data set, and then DLSNE projects the extracted features to a two dimensional graph.

The proposed DESNE is verified on the Tennessee Eastman process and a real data set of blade icing of wind turbines. The results indicate that DESNE outperforms some visualization methods in process monitoring.

This paper has significant originality. A stacked variant auto-encoder is proposed for feature extraction. The stacked variant auto-encoder can improve the separation among classes. A deep label-guided t-SNE is proposed for visualization. A novel visualization-based process monitoring method is proposed.

This study presents a new method for the detection of faults in large transformer cores. It is based on the analysis of leakage flux components in the vicinity of the sheet stack. The purpose of this study is to provide a nondestructive analysis tool for transformer cores during the assembly process to detect accidental defects such as inter-laminar short circuits.

The different components of the leakage flux allow localization of the fault in the stack and also permit to assess its severity. Out of the many kinds of defects which may appear in a transformer core, this method only detects those which actually cause an increase in the transformer’s global iron losses, which are thus the most detrimental.

The proposed method allows a more efficient control of the quality of the cores during their manufacturing process. Until now, it was only possible to know the quality of the core when the transformer was fully assembled.

The accuracy of the method depends on the size of the defect and may request many measurements to give usable information.

Controlling iron losses in a core during its construction avoids heavy dismantling operations, both financially and temporally.

This method can help transformer manufacturers optimize their building process. In addition, the method remains effective regardless of the size of the core considered.

A new concept of 3D‐electronic packaging is presented: Si‐on‐Si multi‐chip module flip‐chip technology with arrays of fine etched and filled vertical electrical interconnections (vias). Arrays of vias with a high number of interconnections, and not only peripheral interconnections are used. A 3D Si‐on‐Si stack package demonstrator has been realized consisting of four Si‐substrates each representing a system level and containing four thinned and flip‐chip assembled chips. The chips are flip‐chip mounted on the flat side of the Si‐substrates. When interconnecting the Si‐substrates by bump technology the chips submerge into cavities on the rear side of the adjacent Si‐substrate. The chips also test the technology and quality of the electronic packaging, and therefore contain a set of thin film heaters, junctions for temperature measuring, Al‐meanders for stress and strain measuring and daisy chains for conduction path monitoring.

Antiwear mechanism of action of some chemical elements added to lubricant is studied. These elements are transferred from the lubricant into the surface layers of the sliding pair during friction. The mechanism is based on the influence of these elements on the stacking fault energy (SFE) of the materials in the friction pair and leads to changes in the fragmented structure formed in the metals under plastic deformation. Work hardening of the metal surface layers and their predisposition to wear are changed accordingly. Copper and Armco iron, as typical FCC and BCC metals, were chosen for the friction pair materials. Si, Ni, Zn, Co and Ti were used as the additive components to the lubricant. It was found that the addition of different elements to the lubricant leads to alloying by these elements of the surface layers of the metal during the process of friction. It was found that alloying by elements which decreases the SFE of the metal, the average size of surface layer fragments formed during friction increases and the wear rate decreases. The possibility of controlling the wear resistance of metals during friction through the use of appropriate additives is discussed.