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The Center for Industrial Research (SI), the University of Oslo (UiO) and a group of Norwegian companies have collaborated between 1990 and 1992 in the research programme ‘Industrial Microelectronics’ with a total cost of 30 MNOK. The programme was sponsored by the Norwegian Scientific and Industrial Research Council (NTNF) as one of the twin programmes constituting a national research initiative in microelectronics. The motivation for the programme is the recognition of microelectronics as a key technology commanding the performance and market success of many of the electronics systems from the Norwegian electronics industry towards the year 2000. The main objective is to stimulate industrial innovation by developing, transferring and exploiting knowledge and methods based upon advanced microelectronics. Focused activities are silicon sensor technology, combined analogue/digital design of application‐specific integrated circuits, large scale instrumentation, sensor packaging and thermal management of electronic systems. SI is focusing on applied research, UiO on education, and collaborating Norwegian companies are using the results in their own R&D projects. It is anticipated that the research results will be fully industrialised within 3–5 years. The programme is co‐ordinated with other Norwegian government‐sponsored research activities as well as European research programmes based on microelectronics. The programme is organised in projects and monitored with a set of milestones strongly indicating the achievement of successful industrial innovation, research results of international standing and high‐quality education of key personnel for the industry. Several successful examples of the research results are highlighted: Design and process methodology for double‐sided microstrip silicon radiation sensors for detection of high energy elementary particles, silicon‐to‐silicon and silicon‐to‐thin film anodic bonding processes for sensor fabrication, combined analogue/digital application‐specific integrated circuits for front‐end instrumentation applications, packaging of radiation sensors and thermal management of electronic systems by evaporation cooling. It is concluded that the programme has successfully achieved results in harmony with the objective.

Silicon sensors are semiconductor devices which transform a physical effect (such as pressure, acceleration, flux) into electrical effects (resistance, capacitance variation). Fabrication of these silicon sensors requires very precise control of the silicon micromachining. Some silicon foundries have adapted their experience in integrated circuit manufacturing to silicon sensor production and thus have reduced the costs and dimensions of the silicon sensors. Standard thick film technology has brought versatility to silicon sensor technology. Silicon sensors mounted on a ceramic substrate give fast development, high performance and low cost to OEMs. An alternative solution is the integrated silicon sensor including sensor and circuitry on the same silicon chip. This has been developed for specific applications.

Whatever one may feel is the importance of particular interconnection and assembly technologies with which one is associated, Thin Film or Thick Film Hybrid, PCB Through Hole, Surface Mounting, etc., the driving force in electronics is the high degree of low cost functionality brought by semiconductor technology. However, semiconductor science cannot provide systems solutions on its own and needs to be combined with suitable interconnection and assembly technologies to bring its potential processing power to fulfilment. Hybrid technology holds a key role in the use of silicon in overall system integration. On hybrid substrates semiconductors can be applied in any of the forms available, from bare dice to encapsulated, tested and burnt‐in complex functions in LSI. Over the years hybrids have developed, needing semiconductors as the active elements in providing functional modules. The relationship between the technologies has been close but not always in perfect harmony at the commercial interfaces. The first part of this paper reviews development of semiconductors in relation to the forms of packaging available for application in hybrid assembly including the emergent means being adopted to tackle the problems of ever increasing lead counts that will be with us for some time until the dream of total self‐sufficiency on silicon becomes a reality. The second part of the paper reviews silicon design options with the emphasis on the relevance of combining silicon implementation with hybrid methods.

The purpose of this paper is to examine how entrepreneurship culture affects start-up and venture capital co-evolution during the early evolution of an entrepreneurial ecosystem (EE) and its ability to foster the emergence of ambitious entrepreneurship as an outcome of its activity. Unlike studies that capture entrepreneurship culture at the national level, this study focusses specifically on the culture of venture capital-financed entrepreneurship and understanding its implications to the development of venture capital markets and successful firm-level outcomes within ecosystems.

Relying on EE and organisational imprinting theory, this study specifies characteristics of venture capital-financed entrepreneurship of Silicon Valley to illustrate the American way of building start-ups and examine whether they have as imprints affected to the entrepreneurship culture and start-up and venture capital co-evolution in Finland during the early evolution of its EE between 1980 and 1997.

The results illustrate venture capital-financed entrepreneurship culture as a specific example of entrepreneurship culture beneath the national level that can vary across geographies like the findings concerning Finland demonstrate. The findings show that this specific culture matters through having an impact on the structural evolution and performance of EEs and on the ways how they deliver or fail to deliver benefits to entrepreneurs.

The results show that venture capital-financed entrepreneurship and the emergence of success stories as outcomes of start-up and venture capital co-evolution within an EE are connected to a specific type of entrepreneurship culture. This paper also contributes to the literature by connecting the fundamentals of organisational imprinting to EE research.

In this paper, the authors aim to examine some characteristics of the innovation system and policy in France and China. For comparison, they also highlight some high technology features of Silicon Valley and California.

The authors study the characteristics of innovation in France and in China. The authors examine the technology systems and policies in both countries and compare their features with those in Silicon Valley.

As far as France is concerned, it can be stated that the innovation system and policy are under transformation, going from a strong state involvement to a more decentralized framework. This evolution leads to a multi-level governance of the innovation system and to the emergence of new actors. For China, the most interesting development in China is the evolution of its internet-related sector. The authors argue here that the internet-driven economy is a radical, systemic technological change and it is rapidly growing in China.

One of the earliest papers comparing the innovation policies and activities in France, China and Silicon Valley.

A review of integrated optical circuit technologies [OIC] and their relevance to potential OIC sensor application. Describes the manufacture of OICs and the varied range of material technologies used. Active Silicon Integrated Optical Circuits have been developed which may have applications for many optical sensor and fibre optic sensor systems. Concludes however that silicon integrated optics will not enjoy large‐scale success until their manufacturing costs have been dramatically reduced.

Experts claim over 50% of sensor applications are currently served by silicon‐sensor technology.

Reviews intelligent structures through surface‐ and bulk‐micromachining. Examines the merits of these techniques and their past, present and future applications to real‐life problems.

The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials and manufacturers as Intel or IBM to boost the performances of the nanoscale PMOS and NMOS transistors. It is now admitted that compressive stress enhances the mobility of holes and tensile stress enhances the mobility of electrons in the channel.

During thermal processing, thin film materials like polysilicon, silicon nitride, silicon dioxide, or SiGe expand or contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The author defines the thermal expansion coefficient as the rate of change of strain with respect to temperature.

Several numerical experiments have been used for different temperatures ranging from 30 to 1,000°C. These experiments did show that the temperature affects strongly the extrinsic stress in the channel of a 45 nm PMOS transistor. On the other hand, the author has compared the extrinsic stress due to lattice mismatch with the extrinsic stress due to thermal mismatch. The author found that these two types of stress have the same order (see the numerical results on Figures 4 and 12). And, these are great findings for semiconductor industry.

Front-end process induced extrinsic stress is used by manufacturers of nanoscale transistors as the new scaling vector for the 90 nm node technology and below. The extrinsic stress has the advantage of improving the performances of PMOSFETs and NMOSFETs transistors by enhancing mobility. This mobility enhancement fundamentally results from alteration of electronic band structure of silicon due to extrinsic stress. Then, the results are of great importance to manufacturers and industrials. The evidence is that these results show that the extrinsic stress in the channel depends also on the thermal mismatch between materials and not only on the material mismatch.

The model the author is proposing to calculate the initial stress due to thermal mismatch is novel and original. The author validated the values of the initial stress with those obtained by experiments in Al-Bayati et al. (2005). Using the uniaxial stress generation technique of Intel (see Figure 2). Al-Bayati et al. (2005) found experimentally that for 17 percent germanium concentration, a compressive initial stress of 1.4 GPa is generated inside the SiGe layer.

This paper aims to illustrate how sensors can be fabricated by combining nanomaterials with micro-electromechanical system (MEMS) technology and to give examples of recently developed devices arising from this approach.

Following a short introduction, this paper first identifies the benefits of MEMS technology. It then discusses the techniques for integrating carbon nanotubes with MEMS and provides examples of physical and molecular sensors produced by these methods. Combining other gas-responsive nanomaterials with MEMS is then considered and finally techniques for producing graphene on silicon devices are discussed. Brief concluding comments are drawn.

This shows that many physical and molecular sensors have been developed by combining nanomaterials with MEMS technology. These have been fabricated by a diverse range of techniques which are often complex and multi-stage, but significant progress has been made and some are compatible with standard CMOS processes, yielding fully integrated nanosensors.

This provides an insight into how two key technologies are being combined to yield families of advanced sensors.