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Dealing with forming and tinning in a low‐volume high‐reliability environment is a never‐ending challenge. This process is one of the most critical steps in SMT fabrication. The effects of forming and tinning contribute to a majority of the defects found at final inspection. The intention of this paper is to describe in detail the forming and tinning process and all that it entails. The topics include: forming, tinning, converting to an automated process, process control techniques, and statistical process capability.

To present and discuss open trace defects uncovered in an FR4 assembly during electrical testing.

This paper presents open trace defects observed in FR4 assemblies and analyses the distribution of defects. The paper also discusses possible root causes for their occurrence.

The open trace defects that occurred during printed circuit board (PCB) fabrication should have been observed by the board manufacturer. It appears that the PCB manufacturer did not perform automatic optical inspection (AOI) and electrical testing during the manufacturing of the boards. The cost due to the rejected PCBAs was approximately 3x times that of the PCB cost.

The paper highlights the costly impact of uncovering a PCB defect after assembly. Based on the results of this study, the implementation of electrical testing and AOI for PCBs is recommended.

The International Society for Hybrid Microelectronics invites the submission of technical papers for presentation at the above event. All original unpublished papers on microelectronics related topics are welcomed.

Chicago Laser Systems (CLS) have moved to new headquarters in Des Plaines, a suburb of Chicago, near O'Hare International Airport. The new facility, comprising 52,000ft2, embodies plant and administrative functions, and has space for further growth.

This paper presents an experience in designing a printed circuit board prototype as part of a general surface mount investigation for commercial electronics application. The point of view is that of a low volume assembler of relatively large, complex PC boards which use standard components. Three prototype versions were designed using different criteria. FR‐4 substrate was used for all of the designs. A comparison of the three designs with the through‐hole version indicates that the economic success of surface mounted printed circuit assemblies is heavily dependent on the physical design of the printed circuit board. Some of the aspects of a surface mounted circuit assembly that are discussed include design philosophy and tools, printed circuit board fabrication and bare board test. Design practices that would ideally utilise the small size of surface mount components are contrasted with those practices necessary to provide low cost and manufacturability of the printed circuit board.

Embedded passives technologies can provide benefits of size, performance, cost, and reliability to high density, high‐speed designs. A number of embedded passive technology solutions are available to the designer. Based on our experience with Rohm and Haas's thin‐film, high‐ohmic, InSite^TM embedded resistor materials (500 and 1000 Ω/sq), this paper provides some guidelines for selecting the appropriate embedded resistor technology and implementing it at a board fabricator. The design of embedded resistors, and the trade‐offs between resistor size, tolerance, and capability of board fabrication processes, are analyzed in detail. This paper also discusses selection of the appropriate embedded capacitor technology and introduces some initial results on Rohm and Haas's thin‐film, high‐D_k, InSite embedded capacitor material (200 nF/cm²).

The use of fine‐pitch SMD devices has increased the need for accurate and consistent solder paste deposits for reflow soldering. Continued miniaturisation in PCB and SMD lead sizes is presenting the user, paste supplier and print equipment manufacturer with paste printing challenges. Most of these challenges are user‐driven, and are generally met by enhancing associated print equipment and solder paste materials. Recent developments in fine‐particle pastes, water‐soluble and no‐clean pastes are among the improvements in materials. Vision‐assisted stencil aperture and PCB pad alignment, the use of metal squeegees and new stencil fabrication methods are among the latest developments on the equipment side. Printing tests have shown that there is a physical limit for the solder paste printing process, which is defined partly by the nature of the stencil fabrication process, the physical forces and the stencil's ability to meter a precise volume of paste. The challenge as SMD lead sizes decrease is to improve the printing process to match component lead sizes. There is a fear that we are now operating at the very limits of the solder paste printing process. To meet future component developments, there is a need to develop alternative printing processes for solder reflow.