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This paper aims to present an effective approach to integrated circuit (IC) throughput enhancement, called TΔT thermal control. It does not require any micro-architectural change of the IC. The only modification is the attachment of an additional temperature sensor at the heatsink boundary. TΔT control technique enables assessment of changes in the dimension of cooling conditions and quick reaction to the dynamic changes in the surrounding environment. As a result, the chip can operate flexibly while minimizing thermal violation.

Using additional knowledge about the surroundings, the on-chip temperature is regulated. The approach is first investigated theoretically. To validate the utilized thermal model, the measured temperature values of the designed and fabricated testing device are compared with the simulated one. The authors evaluated the impact of the additional sensor location on the reaction time (RT). Using the Spice model, further investigation helps to verify the hypothesis.

The control technique described in this paper showed that the temperature of the chip can be regulated using an additional knowledge of the surrounding environment. It has also been demonstrated that the attachment of an additional temperature sensor close to the cooled surface of the package enables TΔT thermal control technique to react faster (rapid powering up/down of the IC). Therefore, this lowers the risk of shutdown while keeping the temperature close to the thermal limit (the maximal temperature of the chip) for a significant period. The simulation results showed that a higher ambient temperature leads to diminution of the interval in which the on-chip temperature stays almost constant when TΔT technique is used (time shift).

In this study, a new thermal throttling technique that uses the full physical ability of the chip operating under thermal constraint has been evaluated.

This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS).

Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology.

Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable to dynamic energy losses, use of dynamic voltage frequency scaling can even lead to increased energy consumption.

This paper presents complete analysis of energy losses in CMOS circuits and effectiveness of mentioned methods of energy conservation in CMOS circuits in six different technologies.