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This article aims to present complete analysis of energy losses in complementary metal-oxide semiconductor (CMOS) circuits and the effectiveness of dynamic voltage and frequency scaling (DVFS) as a method of energy conservation in CMOS circuits in variety of technologies. Energy efficiency in CMOS devices is an issue of highest importance with still continuing technology scaling. There are powerful tools for energy conservation in form of dynamic voltage scaling (DVS) and dynamic frequency scaling (DFS).

Using analytical equations and Spice models of various technologies, energy losses are calculated and effectiveness of DVS and DFS is evaluated for every technology.

Test showed that new dedicated technology for low static energy consumption can be as economical as older technologies. The dynamic voltage and frequency scaling are most effective when there is a dominance of dynamic energy losses in circuit. In case when static energy losses are comparable to dynamic energy losses, use of dynamic voltage frequency scaling can even lead to increased energy consumption.

This paper presents complete analysis of energy losses in CMOS circuits and effectiveness of mentioned methods of energy conservation in CMOS circuits in six different technologies.

In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications.

The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit.

The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased.

The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

Gives introductory remarks about chapter 1 of this group of 31 papers, from ISEF 1999 Proceedings, in the methodologies for field analysis, in the electromagnetic community. Observes that computer package implementation theory contributes to clarification. Discusses the areas covered by some of the papers ‐ such as artificial intelligence using fuzzy logic. Includes applications such as permanent magnets and looks at eddy current problems. States the finite element method is currently the most popular method used for field computation. Closes by pointing out the amalgam of topics.

The purpose of this paper is to characterize the nonlinear dynamical behaviour of a buck‐based power‐switching amplifier controlled by fixed frequency and pulse width modulation with a proportional‐integral compensator. The system has two forcing frequencies and one natural frequency and therefore it is characterized by three different scales of time. When the frequencies are far one from the other, quasi‐static approximation can be used. However, as the switching and the modulating frequencies become closer, this approximation is not valid and the results based on it lead to erroneous conclusions about the dynamics of the system.

A discrete time approach is used to reveal the interesting nonlinear phenomena that the system can exhibit. From numerical simulations using the switched model, it is shown that the system can present period‐doubling bifurcation at the fast scale (switching frequency).

An exact solution discrete‐time model is derived, able to predict accurately the nonlinear dynamical behaviour of the system.

The discrete time model is obtained without making quasi‐static approximation. The exact switched model is used to validate the discrete‐time model obtained. Finally, the effect of the switching frequency instabilities on the output voltage spectrum has been explored.

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

This paper sets out to design and realize a highly linear, wide dynamic range and high switching efficiency integrated CMOS up‐conversion mixer for two‐step IEEE 802.1a WLAN transmitter application in 0.18‐μm deep submicron CMOS technology.

A folded current draining low‐voltage mixer architecture is explored and an extensive simulation carried out utilizing Cadence Spectre‐RF tool in optimizing the linearity, input third‐order intercept point (IIP3), the dynamic range, 1 dB compression point (P_−1dB), power dissipation and reduction of switching quad C_gs, input gate‐source capacitance, in enhancing the switching efficiency of the proposed architecture.

A highly linear, high input dynamic range, low voltage folded up‐conversion mixer architecture is realized in a significant comparable performance with respect to conventional reported architecture, indicating −8.87 dBm of OIP3 corresponding to 15.27 dBm IIP3 and 4.37 dBm of P_−1dB in 0.18‐μm CMOS technology.

The optimized mixer architecture is stringent to an up‐converter application. To be utilized as a down converter at the receiver end, parameters, namely as noise figure and conversion gain, are of additional importance.

The designed folded mixer architecture is in need of integration to a two‐step up‐conversion transmitter architecture which relaxes the injection pulling effect for a given low voltage headroom, with low power dissipation design.

In this work, an integrated folded architecture with on‐chip process, voltage and temperature compensated biasing circuit is explored and enhanced, raising awareness of adapting improved multiplier blocks in achieving optimal performance in WLAN transceiver architecture.

The article explores the effect of sintering temperature on the ferroelectric hysteresis behavior of the synthesized ceramic material Ba_0.9Ca_0.05Sr_0.05T_0.85Zr_0.15O₃ (BCSTZO). It describes how the sintering temperature and its holding time have effect on the polarization-electric field (P-E) loops which is an important characteristic of a ferroelectric material. From the P-E loops obtained, various representative parameters like remnant polarization and coercive field values were extracted and scaling results were systematically established using them.

The present article describes the establishment of scaling relations for coercive field (E_c), remnant polarization (P_r) and back switching polarization (P_bc) as a function of temperature which have been obtained from P-E loops sintered at various temperature and time. This is because sintering temperature plays a pivotal role in determining the hysteresis parameters.

The temperature dependent scaling of Ec and Pr at sintering temperature of 1400, 1425, 1450 and 1475 °C yields E_cαT^0.40, E_cαT^0.80, E_cαT^0.47, E_cαT^0.29 and P_rαT^−1.72, P_rαT^−1.55, P_rαT^−1.72, P_rαT^−1.69 respectively. Further the scaling relations for the samples sintered at 1450 °C at different time interval of 3, 4, 5 and 6 h was also established to bring the effect of sintering in switching the ferroelectric hysteresis parameters.

The findings of this work will prove beneficial for the researchers working in optimization of sintering parameters and will benefit researchers selecting best material among the fabricated samples for further property enhancement. The optimized sample could be explored for multifunctional applications ranging from pyroelectric voltage to piezoelectric energy harvesting. In addition to this, the scaling results help to understand the nature of ferroelectric parameters with sintering. This may open up new avenues for studying the scaling behavior of dynamic hysteresis in synthesized material by focusing on hysteresis area as a function of applied electric fields, frequency and temperature. This reason owes to the fact that electric field and frequency are important parameters for a number of applications like sensor, transducers and medical applications.

Introduces papers from this area of expertise from the ISEF 1999 Proceedings. States the goal herein is one of identifying devices or systems able to provide prescribed performance. Notes that 18 papers from the Symposium are grouped in the area of automated optimal design. Describes the main challenges that condition computational electromagnetism’s future development. Concludes by itemizing the range of applications from small activators to optimization of induction heating systems in this third chapter.

Based on the positive features of the shark smell optimization (SSO) algorithm, the purpose of this paper is to propose a method based on this algorithm, dynamic voltage and frequency scaling (DVFS) model and fuzzy logic to minimize the energy consumption of integrated circuits of internet of things (IoT) nodes and maximize the load-balancing among them.

Load balancing is a key problem in any distributed environment such as cloud and IoT. It is useful when a few nodes are overloaded, a few are under-loaded and the remainders are idle without interrupting the functioning. As this problem is known as an NP-hard one and SSO is a powerful meta-hybrid method that inspires shark hunting behavior and their skill to detect and feel the smell of the bait even from far away, in this research, this study have provided a new method to solve this problem using the SSO algorithm. Also, the study have synthesized the fuzzy logic to counterbalance the load distribution. Furthermore, DVFS, as a powerful energy management method, is used to reduce the energy consumption of integrated circuits of IoT nodes such as processor and circuit bus by reducing the frequency.

The outcomes of the simulation have indicated that the proposed method has outperformed the hybrid ant colony optimization – particle swarm optimization and PSO regarding energy consumption. Similarly, it has enhanced the load balance better than the moth flame optimization approach and task execution node assignment algorithm.

There are many aspects and features of IoT load-balancing that are beyond the scope of this paper. Also, given that the environment was considered static, future research can be in a dynamic environment.

The introduced method is useful for improving the performance of IoT-based applications. We can use these systems to jointly and collaboratively check, handle and control the networks in real-time. Also, the platform can be applied to monitor and control various IoT applications in manufacturing environments such as transportation systems, automated work cells, storage systems and logistics.

This study have proposed a novel load balancing technique for decreasing energy consumption using the SSO algorithm and fuzzy logic.

The Purpose of this research is to make an energy efficient finite state machine (FSM) in order to achieve the core objective of green computing because FSM is an indispensable part of multiple computer hardware.

This study uses ultra-scale plus FPGA architecture in place of seven-series field-programmable gate array (FPGA) for the implementation of the FSM design and also uses output load scaling for the design of environment-friendly FSM. This design study is done using Verilog Hardware description language and Vivado integrated system environment design tools and implemented on 16 nm ultra-scale FPGA architecture.

There is up to 98.57% reduction in dynamic power when operating frequency is managed as per smart job scheduling. There is up to a 21.97% reduction in static power with proper management of output load capacitance. There is up to 98.43% saving in dynamic power with the proposed management of output load capacitance.

The proposed design will be environment friendly that eventually leads to the green earth. This is the main motive of the research area i.e. green computing.