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The effect of ultrasonic agitation on hybrid devices during PCB cleaning has long been suspected as leading to device malfunction. However, little or no data exist to substantiate or quantify these effects. This paper describes a limited study into these effects using both test vehicles and commercial products, and discusses their variation with exposure time, the types and mechanisms of failure, and the rle of the hybrid package construction. It is demonstrated that the design of the hybrid package is critical in determining its susceptibility to ultrasonic damage.

The effects of ultrasonic agitation on electronic components during PCB cleaning has long been the subject of controversy. This paper summarises the results of a series of studies into these effects for a range of components using CFC, aqueous and semi‐aqueous cleaning media. The variations with exposure time and power density under various ultrasonic stress conditions (loose, mounted on PCBs, or on purpose‐built test boards) are discussed. The results are encouraging and suggest that there is a large margin of safety when employing currently accepted regimes of operation and good quality components. However, the strong dependence of the damage accumulation on power density emphasises the need to specify and tightly control the power density used.

Although the use of ultrasonic agitation on quartz crystal devices during PCB cleaning has long been suspected to be detrimental, little or no data exist to substantiate or quantify the resultant effects. This paper summarises the results of a limited study into these effects for a range of quartz crystal devices, using both CFC and aqueous solvents. The variations with exposure time, and the types and mechanisms of failure are discussed. The results are encouraging and suggest that, although these devices are more susceptible to damage than ICs, once manufacturing defects have been screened out they will withstand ultrasonic exposure without deleterious effects for periods several times longer than those used for cleaning PCBs.

With the advent of the Montreal Protocol, the removal of flux residues from printed circuit assemblies using solvents based on CFC‐113 is no longer an acceptable option. An alternative range of cleaning technologies is being developed and marketed for this purpose, and the aim of this work was to study the efficiency of a variety of these alternative cleaning regimes after IR reflow soldering. The results indicated that: (i) all the cleaning regimes were capable of removing flux and flux residues after standard IR reflow soldering; (ii) as the level of flux contamination under the components increased, the ability of the cleaning regimes to clean the boards decreased; (iii) the cleaning regimes had varying problems in removing the flux residues after the non‐standard (overheat) IR profile processing; (iv) when additional flux is introduced under the components (i.e., non‐standard IR reflow), the delay between soldering and cleaning becomes important; and (v) the cleaning regimes exhibited a wide variation in their ability to clean under components with small stand‐off heights.

An investigation of the use of ultrasonic agitation for cleaning printed circuit boards using CFC‐based solvents has shown that, under the standard conditions required to produce clean assemblies, no damage will occur to the components studied. Damage can only be induced by use of anomalously longer times or higher power densities. In all cases in which damage has been induced, it is of a purely mechanical nature due to fatigue, and is located on the device bond‐wires and/or the package legs. Cleaning using CFC‐based solvents under standard ultrasonic conditions of power density and time etc. is readily achieved within 2 minutes, even with a minimum stand‐off height.

DISCUSSION The chromium coating thicknesses used in this work were comparable to those used commercially, being between 70 and 170 micrometres approximately. Even after oxidation for the temperatures and times stated the chromium concentrations at the metal‐oxide interface were between 20% and 60%. These concentrations fell steadily to approximately 13% over the approximate depth stated above before reducing sharply to zero at what was the ferrite‐austenite transformation boundary during the coating process. This is contrary to the structure observed in aluminized stainless steels where a complex structure is produced due to the existence of intermetallic phases. Hence during all the oxidation experiments performed the chromium level of the surface offered for oxidation was never below 13% and complete oxidative breakdown therefore did not occur, excluding spalling effects. Many workers have shown that the oxidation rate of iron‐chromium alloys initially drops sharply with increasing chromium but eventually reaches a minimum of about 20% chromium and then rises for more chromium rich alloys. From the graph of oxidation rate in pure oxygen against chromium content given by Mortimer et al., from 13% chromium to 100% chromium the oxidation rate increases by approximately 6 × 10−9 g.cm−2 sec.−1 It is reasonable to assume that for a diffusion coating the oxidation behaviour will be markedly affected by the composition at its outer surface layer and much less by the composition gradient. If oxidation was continued for sufficiently long periods the latter could affect the general availability of chromium ions for the oxidation process. Over the first 5?m the average chromium levels were between 63% and 20% for the chromised and chrome‐aluminized respectively. From the figures given by Mortimer et al the oxidation rate of the 63% chromium coating would be expected to be 0.5 × 10−9 g.cm−2 sec−1 greater than the 20% chromium coating on the chrome‐aluminized specimens at 600°C, on the basis of the chromium content alone. The results obtained here vary in this manner, hence it is reasonable to conclude that the general oxidation behaviour of the coatings will be very similar to that of pure iron‐chromium alloys containing the same chromium content as in the outer few micrometres of the respective coatings. Even though the true surface area is greater with diffusion treated specimens their oxidation rates are lower that for the corresponding pure alloys.

The annual Autumn Conference of the British Association for Brazing and Soldering offers a forum for discussions between scientists and engineers involved with two technologies which, because of their obvious similarities, would be expected to be of mutual benefit and learning. In reality both the science and the practice of brazing and soldering are quite different. I suspect, with some regret, the BABS Management Committee decided that for the first time this division be formally recognised by offering soldering as the subject of the first day and brazing and diffusion bonding the subjects of the second. This report covers the soldering day only, during which seven papers were presented:

No‐clean flux printed board appraisal tests were conducted with all materials used in the production process. Metallic growths during environmental testing revealed that there was incompatibility between some materials used. Initial tests with two solder resists and several fluxes showed that one non solder resisted board, soldered using a synthetically activated (SA) flux, had surface insulation resistance (SIR) two decades higher than those using low solids flux (LSF) or other SAs. For boards with solder resist, the SIR of those soldered using LSFs was higher, however, than those using SA fluxes. SIR dependence on temperature and humidity was investigated. Results demonstrated that the dominant factor to determine the SIR of a no‐clean board was the characteristics of the board substrate finish. SIR changes with condensation were logged and found to be significant for solder resist finishes. Tests proved that reducing the contamination levels under and on top of the solder resist, by using hot de‐ionised water rinsing, enabled the calculated minimum SIR level to be achieved for spray fluxed boards and minimised the possibility of metallic growth. Visual examination proved to be at least as important as SIR testing. No‐clean processes were appraised using sequential environmental conditions with differing SIR pass levels. As a result of this appraisal a maximum ionic contamination level of 0·5 μg/cm2 NaCl equivalent and Dl water rinses, before and after solder resist added, will be introduced. Ionic contamination tests indicated that contamination levels reduced with elapsed time, probably due to ionic molecules locking more firmly into the board surface structure. A novel method for SIR measurements at any voltage, developed by the author, is described. It is hoped that this paper will further the understanding of no‐clean flux issues and highlight potential solutions and pitfalls.

The surface insulation resistance (SIR) test has traditionally been performed by taking measurements at certain points during a seven‐day test under well established environmental conditions. The work reported here explores the influence of test temperature and humidity when using a typical resin flux, a weak organic flux and glycol based fluxes when sampling SIR patterns every ten minutes. Results indicate that some fluxes are very sensitive to the test temperature, with volatilisation of flux residues an important issue. The frequent monitoring of the results also permitted the detection of dendrites during the SIR test. The results clearly show the importance of selecting the correct testing conditions and the benefit of frequent monitoring.

SIR testing is in practice carried out under a wider range of experimental conditions than those detailed in standards. The work presented here explores some of the issues when using a range of fluxes with various processing conditions and also examines the influence of substrate finish, test bias and the reflow process. These results clearly show that care must be exercised when using different test set‐ups, and when extrapolating between testing and use conditions. In particular the use of a 50V test bias voltage can produce anomalous results when compared to a 5V use environment.