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Modern electronics is characterised by the increasing level of integration in printed circuit board (PCB) technology and the reduced insulation spacing between adjacent conductors. Surface insulation resistance (SIR) measurement has often been used alone to determine the cleanliness of PCB assembly; however, when proper SIR measurement is used in conjunction with surface leakage current (SLC) measurement, the result can reveal the dynamic nature of surface electrochemical migration (SECM) processes at the microscopic level, and the effect of such processes on product quality and reliability. This paper presents a newly developed measurement methodology, which measures SLC per square unit area at a sampling rate that is orders of magnitude higher than that of conventional SIR measurement methods. It is aimed to capture the transient surge of SLC which is detrimental to the functionality of product.

In the ideal crack model (negligible thickness and an impenetrable barrier to electric current) in eddy‐current testing frame, the field‐flaw is equivalent to a current dipole layer on its surface. This dipole density is the solution of an integral equation with a hyperstrong kernel. This model has shown its efficiency, as well the computing accuracy, as for the CPU time. Furthermore, the case of a current leakage across crack was considered by introducing an equivalent conductivity of the crack. This paper aims at simulating a local varying conductivity. In particular, we focus on a constant piecewise conductivity. In this last case, because of the presence of the hypersingular kernel in the equation, the numerical scheme using the ideal case has to be modified.

To model the differential dc gain, base resistance, and current voltage performance of 4H‐Silicon Carbide (SiC) bipolar junction transistors (BJT) operating at and above room temperature. Accurate modeling will result in improved process efficiency, interpretation of experimental data, and insight into device behavior.

The PISCES two dimensional device simulation program is used to allow for modeling the behavior of 4H‐SiC BJT. The physical material parameters in PISCES such as carrier's mobility and lifetime, temperature dependent bandgap, and the density of states are modified to accurately represent 4H‐SiC. The simulation results are compared with the measured experimental data obtained by others. The comparisons made with the experimental data are for two different devices that are of interest in power electronics and RF applications.

The simulation results predict a dc current gain of about 25 for power device and a gain of about 20 for RF device in agreement with the experimental data. The comparisons confirm the accuracy of the modeling employed.

The simulated current‐voltage characteristics indicate that higher gain may be achieved for 4H‐SiC transistors if the leakage current is reduced.

The simulation work discussed in this paper complements the current research in the design and characterization of 4H‐SiC bipolar transistors. The model presented will aid in interpreting experimental data at a wide range of temperatures.

This paper reports on a new model that provides insight into the device behavior and shows the trend in the dc gain performance important for the design and optimization of 4H‐SiC bipolar transistors operating at or above the room temperature.

The surface insulation resistance (SIR) test has traditionally been performed by taking measurements at certain points during a seven‐day test under well established environmental conditions. The work reported here explores the influence of test temperature and humidity when using a typical resin flux, a weak organic flux and glycol based fluxes when sampling SIR patterns every ten minutes. Results indicate that some fluxes are very sensitive to the test temperature, with volatilisation of flux residues an important issue. The frequent monitoring of the results also permitted the detection of dendrites during the SIR test. The results clearly show the importance of selecting the correct testing conditions and the benefit of frequent monitoring.

A defective printed circuit board assembly that exhibited excessive current leakage was examined to determine the responsible failure mechanisms. Observation of the failure site (determined electrically) by optical and electron microscopy revealed an area in the circuit board where debonded fiber bundles bridged a plated‐through‐hole (PTH) to a copper plane. This phenomenon is highly suggestive of conductive filament formation.

Since the film and its formation is basic to the performance of a coating there are, as might be expected, many studies published yearly on film formation and film properties. Following are typical reports.

I was an invited speaker to the ISHM‐Benelux meeting. As I arrived early, I also sat in on the committee meeting as an observer. Jos B. Peeters was the outgoing president and the incoming committee was widened to about 15 members compared with the previous 6. Following the unanimous election of all those nominated, the committee reconvened and elected Mr Kwikkers as the new president of ISHM‐Benelux. He is a professor at the Technische Hogeschole in Delft.

The purpose of this paper is to investigate the dependence of dark current on threading dislocations (TDs) in relaxed Ge layer for Ge/Si heterojunction photodetectors.

The analysis of the effects of TDs is based on SRH generation and recombination mechanism used in two‐dimensional drift‐diffusion numerical simulation.

It is found that the TDs in Ge layer acting as the recombination centers lead to large dark current densities of devices, and the recombination rate is affected by the impurity out‐diffusion from Si substrate. Besides, the TDs, being the acceptor‐like defects simultaneously, form band barrier at Si/Ge interface with lightly doped Si substrates, thus limiting the minority carrier transport and resulting in low dark current densities.

The simulation results are excellently consistent with the experimental data and indicate that the reduction of threading dislocation densities (TDDs), especially in Ge buffer layer, dramatically decreases dark currents densities of Ge/Si photodetectors. The investigation can be applied to imbue devices with desired characteristics.

Two die attach adhesive products, manufactured by Furane Products Co., claim to meet the military specification for epoxy electronic adhesives (MIL‐STD‐883C, Method 5011) without exception. The products are EPIBOND 7002 which is a thermally conductive adhesive and EPIBOND 7200, an electrically and thermally conductive die attach adhesive. Both are 100% solids and contain no solvents or diluents. Consequently, the likelihood of outgassing and void formation is greatly reduced. Both are extremely high purity systems, and have a hot die‐shear strength of over 6,000 N/M2 at 150°C. Both materials are screen printable and undergo virtually no bleed‐out during processing.

The aim of this paper is to formulate the effect of the process variation on various leakage currents and subthreshold swing factor in FinFET devices. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies.

Owing to large temperature variation within the die, the authors investigate the variation of various leakage currents with absolute die temperature.

The results obtained on the basis of the model are compared and contrasted with reported numerical and experimental results. A close match was found which validates the analytical approach.

The analytical modeling of subthreshold leakage current, subthreshold swing, gate leakage current and its variation with process parameters are carried out in this paper.