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Packages for multichip modules in military airborne applications must hava some fundamental characteristics: high thermal conductivity, low density, good mechanical properties and a coefficient of thermal expansion nearly equal to that of the microelectronic substrate installed in the package. In many cases, the substrate is alumina with a CTE of 6.5 ppm/°C. Materials such as aluminium, titanium or Kovar fulfil only part of the above requirements. This is critical when large packages are used, such as in electronic warfare systems where modules include wideband RF circuits with large alumina substrates next to dense digital circuits. The solution is then aluminium/ silicon carbide (Al/SiC). The aim of the paper is to present the development and qualification of large packages combining both RF and digital circuitry. The size taken into account in the study is 220 × 220 mm: it covers most of the electronic needs in terms of surface. Various aspects have been analysed from the perspective of the package manufacturer and the end‐user. The interest of Al/SiC is shown by a thermal analysis of a conduction cooled module with different core materials: the reduction in temperature gradient, which for some components reaches 20° C, has a strong effect on the module reliability. The different technological choices, for a first type of packages, are described: an Al/SiC baseplate with an iron‐nickel alloy for the ring and the lid, brazed feedthroughs (within the Al/SiC baseplate) and connectors, surface treatment, ring brazing material, lid welding technique. A second type of packages is also presented: the main difference lies in the interconnections. RF ceramic (HTCC) inserts are introduced in the ring frame. Various RF measurements show the interest of the different package technologies, especially the ceramic inserts with very good results up to 20 GHz.

ISHM invites papers for the above Conference, to be held on 29–31 May 1991 in Rotterdam, The Netherlands. Papers should cover areas such as: design, manufacturing, packaging and interconnection, materials and processing, applications, reliability, components, new technologies, marketing and economics, optoelectronics. Summaries should be in English, length 200–300 words. The deadline for receipt of summaries is 30 September 1990. (For full details, see announcement on pp. 54–55.)

ISHM‐Benelux has recently set up a permanent secretariat at the following address:

The venue for this year's ISHM‐Benelux Autumn Conference and ‘table‐top’ display meeting on 12 October will be the Institut Supérieur Industriel de l'Etat, Mons, Belgium.

The purpose of this paper is to introduce a novel computational method to evaluate damage accumulation in a solder joint of an electronic package, when exposed to operating temperature environment. A procedure to implement the method is suggested, and a discussion of the method and its possible applications is provided in the paper.

Methodologically, interpolated response surfaces based on specially designed finite element (FE) simulation runs, are employed to compute a damage metric at regular time intervals of an operating temperature profile. The developed method has been evaluated on a finite-element model of a lead-free PBGA256 package, and accumulated creep strain energy density has been chosen as damage metric.

The method has proven to be two orders of magnitude more computationally efficient compared to FE simulation. A general agreement within 3 percent has been found between the results predicted with the new method, and FE simulations when tested on a number of temperature profiles from an avionic application. The solder joint temperature ranges between +25 and +75°C.

The method can be implemented as part of reliability assessment of electronic packages in the design phase.

The method enables increased accuracy in thermal fatigue life prediction of solder joints. Combined with other failure mechanisms, it may contribute to the accuracy of reliability assessment of electronic packages.

Drive east from Frankfurt, upstream along the valley of the River Main, and in 25 kilometres or so you will reach Hanau, where once the brothers Grimm lived and collected the folklore which we now know as the famous Tales. Here too, in 1856, Wilhelm Carl Heraeus, a chemist and pharmacist, proprietor of the pharmacy which had carried the family name for many generations, succeeded in producing temperatures approaching 2000°C from an oxy‐hydrogen flame, temperatures sufficiently high to achieve the melting point of platinum and to allow him to melt substantial quantities of this metal for the first time. Hanau was then a centre for the jewellery manufacturing industry (and remains so today) so the smelting of platinum and other precious metals had an immediate commercial relevance.

The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type electronic packages. This makes it difficult for conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirements. Therefore, in this study a novel solder joint protection‐WLCSP (SJP‐WLCSP) structure is proposed to overcome the reliability issue.

The SJP‐WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP‐WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer.

To elucidate the thermo‐mechanical behaviour of tin‐lead eutectic solder joints and copper traces, a non‐linear analysis, based on a 3D finite element (FE) model, under accelerated thermal test loadings was carried out. The maximum equivalent stress/strain in the solder joints predicted by the FE simulation were found to diminish significantly when applying the delaminating layer. In addition, parametric FE analysis was also applied in this study, and based on the design concepts within this study, a robust novel SJP‐WLCSP could be achieved.

In this work, a new packaging concept with high reliability, low cost and easy fabrication was developed to reduce the shear stress in the solder joints due to the CTE mismatch between silicon chips and organic PCBs.

The members of the chapter at the annual meeting held on 27 November 1992 in Brno decided not to split after the separation of Czechoslovakia. It was suggested to organise a larger chapter from the Central European States to provide greater co‐operation and better functioning of the smaller chapters. A new name for the chapter was proposed — Central European Chapter (CEC) — to express neutrality and to point out that the chapter is open to other neighbouring chapters and to new members from the states where no national chapter yet exists.

The wafer level package (WLP) is a cost‐effective solution for electronic packaging and has been increasingly applied in recent years. The purpose of this paper is to propose a newly developed packaging technology, based on the concepts of the WLP, the panel base package (PBP) technology, in order to further obtain the capability of signal fan‐out for fine‐pitched integrated circuits (ICc).

In the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface and the pitch of the chip side is fanned‐out. The design concept and the manufacturing process of the PBP would first be described in this study. The three‐dimensional finite element model is established based on the real testing sample and the thermo‐mechanical behavior of the PBP is simulated.

It is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer. However, the accumulated stress/strain from the coefficient of thermal expansion mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid stress concentration effects.

In this paper, a low‐cost and short time‐to‐market packaging technology is proposed which is especially suitable for high density IC devices. The PBP technology has the ability to meet the requirements of major reliability testing conditions and it will have a high potential for application in the near future.

Dates: 29–31 May 1991 Venue: De Doelen Conference Centre, Rotterdam, The Netherlands The Benelux Chapter of the International Society for Hybrid Microelectronics will be organising the 8th European Microelectronics Conference. The event will take place at ‘De Doelen’, Rotterdam, The Netherlands, from 29 to 31 May 1991.