Search results

This paper aims to investigate voiding phenomena in solder joints under thermal pads of light-emitting diodes (LEDs) assembled in mass production environment by reflow soldering by using seven low-voiding lead-free solder pastes.

The solder pastes investigated are of SAC305 type, Innolot type or they are especially formulated by the manufacturers on the base of (SnAgCu) alloys with addition of some alloying elements such as Bi, In, Sb and Ti to provide low-void contents. The SnPb solder paste – OM5100 – was used as a benchmark. The solder paste coverage of LED solder pads was chosen as a measure of void contents in solder joints because of common usage of this parameter in industry practice.

It was found that the highest coverage and, related to it, the least void contents are in solder joints formed with the pastes LMPA-Q and REL61, which are characterized by the coverage of mean value 93.13% [standard deviation (SD) = 2.72%] and 92.93% (SD = 2.77%), respectively. The void diameters reach the mean value equal to 0.061 mm (SD = 0.044 mm) for LMPA-Q and 0.074 mm (SD = 0.052 mm) for REL61. The results are presented in the form of histograms, plot boxes and X-ray images. Some selected solder joints were observed with 3D computer tomography.

The statistical analyses are carried out on the basis of 2D X-ray images with using Origin software. They enable to compare features of various solder pastes recommended by manufacturers as low voiding. The results might be useful for solder paste manufacturers or electronic manufacturing services.

This study aims to address the problem of low-temperature wave soldering in industry production with Sn-9Zn-2.5 Bi-1.5In alloys and develop qualified process parameters. Sn–Zn eutectic alloys are lead-free solders applied in consumer electronics due to their low melting point, high strength, and low cost. In the electronic assembly industry, Sn–Zn eutectic alloys have great potential for use.

This paper explored developing and implementing process parameters for low-temperature wave soldering of Sn–Zn alloys (SN-9ZN-2.5BI-1.5 In). A two-factor, three-level design of the experiments experiment was designed to simulate various conditions parameters encountered in Sn–Zn soldering, developed the nitrogen protection device of waving soldering and proposed the optimal process parameters to realize mass production of low-temperature wave soldering on Sn–Zn alloys.

The Sn-9Zn-2.5 Bi-1.5In alloy can overcome the Zn oxidation problem, achieve low-temperature wave soldering and meet IPC standards, but requires the development of nitrogen protection devices and the optimization of a series of process parameters. The design experiment reveals that preheating temperature, soldering temperature and flux affect failure phenomena. Finally, combined with the process test results, an effective method to support mass production.

In term of overcome Zn’s oxidation characteristics, anti-oxidation wave welding device needs to be studied. Various process parameters need to be developed to achieve a welding process with lower temperature than that of lead solder(Sn–Pb) and lead-free SAC(Sn-0.3Ag-0.7Cu). The process window of Sn–Zn series alloy (Sn-9Zn-2.5 Bi-1.5In alloy) is narrow. A more stringent quality control chart is required to make mass production.

In this research, the soldering temperature of Sn-9Zn-2.5 Bi-1.5In is 5 °C and 25 °C lower than Sn–Pb and Sn-0.3Ag-0.7Cu(SAC0307). To the best of the authors’ knowledge, this work was the first time to apply Sn–Zn solder alloy under actual production conditions on wave soldering, which was of great significance for the study of wave soldering of the same kind of solder alloy.

Low-temperature wave soldering can supported green manufacturing widely, offering a new path to achieve carbon emissions for many factories and also combat to international climate change.

There are many research papers on Sn–Zn alloys, but methods of achieving low-temperature wave soldering to meet IPC standards are infrequent. Especially the process control method that can be mass-produced is more challenging. In addition, the metal storage is very high and the cost is relatively low, which is of great help to provide enterprise competitiveness and can also support the development of green manufacturing, which has a good role in promoting the broader development of the Sn–Zn series.

The purpose of this paper is to develop and test the thermal interface materials (TIM) for application in assembly of semiconductor chips to package. Good adhesion properties (>5 MPa shear strength) and low thermal interface resistance (better than for SAC solders) are the goal of this research.

Mechanical and thermal properties of TIM joints between gold plated contacts of chip and substrate were investigated. Sintering technique based on Ag pastes was applied for purpose of this study. Performance properties were assessed by shear force tests and thermal measurements. Scanning electron microscopy was used for microstructural observations of cross-section of formed joints.

It was concluded that the best properties are achieved for pastes containing spherical Ag particles of dozens of micrometer size with flake shaped Ag particles of few micrometers size. Sintering temperature at 230°C and application of 1 MPa force on the chip during sintering gave the higher adhesion and the lowest thermal interface resistance.

The new material based on Ag paste containing mixtures of Ag particles of different size (form nanometer to dozens of microns) and shape (spherical, flake) suspended in resin was proposed. Joints prepared using sintering technique and Ag pastes at 230°C with applied pressure shows better mechanical and thermal than other TIM materials such as thermal grease, thermal gel or thermally conductive adhesive. Those material could enable electronic device operation at temperatures above 200°C, currently unavailable for Si-based power electronics.

The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu₃Sn layer which locate between the intermetallic Cu₆Sn₅ and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu₃Sn and Cu₆Sn₅ do affected seriously by heat, but Ni₃Sn₄ is not affected by heat or moisture.

The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology.

The Cu₆Sn₅ intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu₃Sn IMC. Cu₆Sn₅ IMC will convert to Cu₃Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu₃Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni₃Sn₄ IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni₃Sn₄ IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell.

The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design.

This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology.

The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.