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Information systems and organization structures have been highly interconnected with each other. Over the years, information systems architectures as well as organization structures have evolved from centralized to more decentralized forms. This research looks at the evolution of both information systems and organization structures. In the process, it looks into the impact of computers on organizations, and examines the ways organization structures have changed, in association with changes in information system architectures. It also suggests logical linkages between information system architectures and their “fit” with certain organization structures and strategies. It concludes with some implications for emerging and future organizational forms, and provides a quick review of the effect of the Internet on small businesses traditionally using stand‐alone computers.

Through a single computerized system, the Libraries Information Access System (LIAS) provides integrated access to a range of information functions in support of services at all libraries of the Pennsylvania State University. It supports both academic and administrative needs. Its design facilitates access to all components through a common terminal. In development since 1975 by the University Libraries, LIAS is a fully interactive system, providing immediate information about collections and transactions.

The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and their corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding many-valued (m-ary) extensions for the use in nano systolic networks are introduced. The second part of the paper introduces the implementation of systolic computing using two-to-one controlled switching via carbon-based field emission that were presented in the first part of the paper, and the computational extension to the general case of many-valued (m-ary) systolic networks utilizing many-to-one carbon-based field emission is also introduced.

The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field-emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented.

Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field-emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented.

The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power VLSI circuit design for signal processing applications.

The introduced bijective systolic implementations form new important directions in the systolic realizations utilizing the newly emerging nanotechnologies. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of high performance, minimum power and minimum size.

The purpose of this paper is to introduce new implementations for parallel processing applications using bijective systolic networks and the corresponding carbon-based field emission controlled switching. The developed implementations are performed in the reversible domain to perform the required bijective parallel computing, where the implementations for parallel computations that utilize the presented field-emission controlled switching and their corresponding m-ary (many-valued) extensions for the use in nano systolic networks are introduced. The first part of the paper presents important fundamentals with regards to systolic computing and carbon-based field emission that will be utilized in the implementations within the second part of the paper.

The introduced systolic systems utilize recent findings in field emission and nano applications to implement the functionality of the basic bijective systolic network. This includes many-valued systolic computing via field emission techniques using carbon-based nanotubes and nanotips. The realization of bijective logic circuits in current and emerging technologies can be very important for various reasons. The reduction of power consumption is a major requirement for the circuit design in future technologies, and thus, the new nano systolic circuits can play an important role in the design of circuits that consume minimal power for future applications such as in low-power signal processing. In addition, the implemented bijective systems can be utilized to implement massive parallel processing and thus obtaining very high processing performance, where the implementation will also utilize the significant size reduction within the nano domain. The extensions of implementations to field emission-based many-valued systolic networks using the introduced bijective nano systolic architectures are also presented.

Novel bijective systolic architectures using nano-based field emission implementations are introduced in this paper, and the implementation using the general scheme of many-valued computing is presented. The carbon-based field emission implementation of nano systolic networks is also introduced. This is accomplished using the introduced field emission carbon-based devices, where field emission from carbon nanotubes and nano-apex carbon fibers is utilized. The implementations of the many-valued bijective systolic networks utilizing the introduced nano-based architectures are also presented.

The introduced bijective systolic implementations form new important directions in the systolic realizations using the newly emerging nano-based technologies. The 2-to-1 multiplexer is a basic building block in “switch logic,” where in switch logic, a logic circuit is realized as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less costly in synthesizing multiplexer-based wide variety of modern circuits and systems since nano implementations exist in very compact space where carbon-based devices switch reliably using much less power than silicon-based devices. The introduced implementations for nano systolic computation are new and interesting for the design in future nanotechnologies that require optimal design specifications of minimum power consumption and minimum size layout such as in low-power control of autonomous robots and in the adiabatic low-power very-large-scale-integration circuit design for signal processing applications.

This paper investigates the integration of leadership training into IT curricula to develop current and future skills needed by the IT job market. The technical and non-technical skills required for IT professionals are presented and a conceptual model for including leadership training in technical courses is outlined. To implement this model, we adopted the Problem-Based Learning approach to teach an IT course. Qualitative and quantitative data were gathered, through a survey, from 52 undergraduate students in the College of Information Technology at Zayed University. Our results show that our adopted approach was successful in teaching IT skills as well as developing leadership skills. Given these findings, we highlight the importance and feasibility of integrating leadership development on a daily basis within technical courses to develop both the technical and non technical skills required by the job market.

As the field of Computer Science (CS) continues to diversify and expand, the need for undergraduates to explore career possibilities and develop personalized study paths has never been greater. This reality presents a challenge for CS departments. How do the students striving to become competent professionals in an ever-changing field of study? How do they do this efficiently and effectively? This study addresses such questions by introducing RadGrad, an online application combining features of social networks, degree planners and serious games.

RadGrad application is designed to promote participation in extracurricular activities, value real-world experience and provide guidance for students planning their degrees. What follows is an exploration of how the application was designed, along with an analysis of how students used it in its first year.

Findings suggest RadGrad helped students to participate in relevant community activities and take an active role in planning their degrees.

The paper describes the features of the application, introducing how the concept of Innovation, Competence and Experience (ICE) scores – rather than a GPAs – were used to motivate undergraduates to participate in extracurricular activities. Initial results suggest RadGrad and the concept ICE scores can be applied to any field where students are encouraged to gain real-world experience as part of their degree program. Lessons learned and future directions are discussed.

New approaches for non‐classical neural‐based computing are introduced. The developed approaches utilize new concepts in three‐dimensionality, invertibility and reversibility to perform the required neural computing. The various implementations of the new neural circuits using the introduced paradigms and architectures are presented, several applications are shown, and the extension for the utilization in neural‐systolic computing is also introduced.

The new neural paradigms utilize new findings in computational intelligence and advanced logic synthesis to perform the functionality of the basic neural network (NN). This includes the techniques of three‐dimensionality, invertibility and reversibility. The extension of implementation to neural‐systolic computing using the introduced reversible neural‐systolic architecture is also presented.

Novel NN paradigms are introduced in this paper. New 3D paradigm of NL circuits called three‐dimensional inverted neural logic (3DINL) circuits is introduced. The new 3D architecture inverts the inputs and weights in the standard neural architecture: inputs become bases on internal interconnects, and weights become leaves of the network. New reversible neural network (RevNN) architecture is also introduced, and a RevNN paradigm using supervised learning is presented. The applications of RevNN to multiple‐output feedforward discrete plant control and to reversible neural‐systolic computing are also shown. Reversible neural paradigm that includes reversible neural architecture utilizing the extended mapping technique with an application to the reversible solution of the maze problem using the reversible counterpropagation NN is introduced, and new neural paradigm of reversibility in both architecture and training using reversibility in independent component analysis is also presented.

Since the new 3D NNs can be useful as a possible optimal design choice for compacting a learning (trainable) circuit in 3D space, and because reversibility is essential in the minimal‐power computing as the reduction of power consumption is a main requirement for the circuit synthesis of several emerging technologies, the introduced methods for non‐classical neural computation are new and interesting for the design of several future technologies that require optimal design specifications such as three‐dimensionality, regularity, super‐high speed, minimum power consumption and minimum size such as in low‐power control, adiabatic signal processing, quantum computing, and nanotechnology.

In order to remain competitive, businesses need to rely heavily on the productivity utilization of microcomputer technology. Microcomputer manufacturers have responded to this need with such a dazzling array of computers and optional equipment that it is becoming progressively more difficult to choose the most appropriate machine. Assists managers with the specification, selection and acquisition of microcomputers. The selection process includes profiling the user, and understanding key computer components and options including physical size, chip features and power, data bus pathways, memory, video, keyboard, mouse, price, acquisition sources, and vendor support services. Understanding what these items are, how they work, and how they work together enables managers to make informed choices relative to hardware acquisition.

The purpose of this paper is to introduce an approach for m‐valued classical and non‐classical (reversible and quantum) optical computing. The developed approach utilizes new multiplexer‐based optical devices and circuits within switch logic to perform the required optical computing. The implementation of the new optical devices and circuits in the optical regular logic synthesis using new lattice and systolic architectures is introduced, and the extensions to quantum optical computing are also presented.

The new linear optical circuits and systems utilize coherent light beams to perform the functionality of the basic logic multiplexer. The 2‐to‐1 multiplexer is a basic building block in switch logic, where in switch logic a logic circuit is implemented as a combination of switches rather than a combination of logic gates as in the gate logic, which proves to be less‐costly in synthesizing wide variety of logic circuits and systems. The extensions to quantum optical computing using photon spins and the collision of Manakov solitons are also presented.

New circuits for the optical realizations of m‐valued classical and reversible logic functions are introduced. Optical computing extensions to linear quantum computing using photon spins and nonlinear quantum computing using Manakov solitons are also presented. Three new multiplexer‐based linear optical devices are introduced that utilize the properties of frequency, polarization and incident angle that are associated with any light‐matter interaction. The hierarchical implementation of the new optical primitives is used to synthesize regular optical reversible circuits such as the m‐valued regular optical reversible lattice and systolic circuits. The concept of parallel optical processing of an array of input laser beams using the new multiplexer‐based optical devices is also introduced. The design of regular quantum optical systems using regular quantum lattice and systolic circuits is introduced. New graph‐based quantum optical representations using various types of quantum decision trees are also presented to efficiently represent quantum optical circuits and systems.

The introduced methods for classical and non‐classical (reversible and quantum) optical regular circuits and systems are new and interesting for the design of several future technologies that require optimal design specifications such as super‐high speed, minimum power consumption and minimum size such as in quantum computing and nanotechnology.