Efficient VLSI architecture for FIR filter design using modified differential evolution ant colony optimization algorithm

Abstract

Purpose

This paper aims to concentrate on an efficient finite impulse response (FIR) filter architecture in combination with the differential evolution ant colony algorithm (DE-ACO). For the design of FIR filter, the evolutionary algorithm (EA) is found to be very efficient because of its non-conventional, nonlinear, multi-modal and non-differentiable nature. While focusing with frequency domain specifications, most of the EA techniques described with the existing systems diverge from the power related matters.

Design/methodology/approach

The FIR filters are extensively used for many low power, low complexities, less area and high speed digital signal processing applications. In the existing systems, various FIR filters have been proposed to focus on the above criterion.

Findings

In the proposed method, a novel DE-ACO is used to design the FIR filter. It focuses on satisfying the economic power utilization and also the specifications in the frequency domain.

Originality/value

The proposed DE-ACO gives outstanding performance with a strong ability to find optimal solution, and it has got quick convergence speed. The proposed method also uses the Software integrated synthesis environment (ISE) project navigator (p.28xd) for the simulation of FIR filter based on DE-ACO techniques.

Citation

John, T.M. and Chacko, S. (2021), "Efficient VLSI architecture for FIR filter design using modified differential evolution ant colony optimization algorithm", Circuit World, Vol. 47 No. 3, pp. 243-251. https://doi.org/10.1108/CW-05-2020-0097