Search results

Traditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.

Rather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.

An ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.

A software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

This paper aims to concentrate on an efficient finite impulse response (FIR) filter architecture in combination with the differential evolution ant colony algorithm (DE-ACO). For the design of FIR filter, the evolutionary algorithm (EA) is found to be very efficient because of its non-conventional, nonlinear, multi-modal and non-differentiable nature. While focusing with frequency domain specifications, most of the EA techniques described with the existing systems diverge from the power related matters.

The FIR filters are extensively used for many low power, low complexities, less area and high speed digital signal processing applications. In the existing systems, various FIR filters have been proposed to focus on the above criterion.

In the proposed method, a novel DE-ACO is used to design the FIR filter. It focuses on satisfying the economic power utilization and also the specifications in the frequency domain.

The proposed DE-ACO gives outstanding performance with a strong ability to find optimal solution, and it has got quick convergence speed. The proposed method also uses the Software integrated synthesis environment (ISE) project navigator (p.28xd) for the simulation of FIR filter based on DE-ACO techniques.

Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.

RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.

In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.

The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

The digital down converter (DDC) is a principal component in modern communication systems. The DDC process traditionally entails quadrature down conversion, bandwidth reducing filters and commensurate sample rate reduction. To avoid group delay, distortion linear phase FIR filters are used in the DDC. The filter performance specifications related to deep stopband attenuation, small in-band ripple and narrow transition bandwidth lead to filters with a large number of coefficients. To reduce the computational workload of the filtering process, filtering is often performed as a two-stage process, the first stage being a down sampling Hoegenauer (or cascade-integrated comb) filter and a reduced sample rate FIR filter. An alternative option is an M-Path polyphase partition of a band cantered FIR filter. Even though IIR filters offer reduced workload to implement a specific filtering task, the authors avoid using them because of their poor group delay characteristics. This paper aims to propose the design of M-path, approximately linear phase IIR filters as an alternative option to the M-path FIR filter.

Two filter designs are presented in the paper. The first approach uses linear phase IIR low pass structure to reduce the filter’s coefficient. Whereas the second approach uses multipath polyphase structure to design approximately linear phase IIR filter in DDC.

The authors have compared the performance and workload of the proposed polyphase structured IIR filters with state-of-the-art filter design used in DDC. The proposed design is seen to satisfy tight design specification with a significant reduction in arithmetic operations and required power consumption.

The proposed design is an alternate solution to the M-path polyphase FIR filter offering very less number of coefficients in the filter design. Proposed DDC using polyphase structured IIR filter satisfies the requirement of linear phase with the least number of computation cost in comparison with other DDC structure.

The purpose of this paper is to improve the performance of control loop suffering from control valve stiction. Control valve stiction is considered as of one of the main causes of oscillation in process variables, which require performing costly unplanned maintenance and process shutdown. An adaptive solution to handle valve stiction while maintaining safety and quality until next planned maintenance is highly desirable to save considerable cost and effort.

This paper implements a new stiction compensation method built using adaptive inverse model techniques and intelligent control theories. Finite impulse response (FIR) model, which is known to be robust, as a compensator for stiction. The parameters of FIR model are tuned in an adaptive way using differential evolution (DE) technique. The performance of proposed method is compared with other two compensation techniques.

The new method showed excellent performance of the DE–FIR compensator compared to other dynamic inversion methods in terms of minimizing process variability, energy saving and valve stem aggressiveness.

The compensation ability for all compensators reduces with the increase of stiction severity, thus the over shoot case always shows the worst result. In future works, other optimization techniques will be explored to find the appropriate technique that can extend the FIR model size with smallest computation time that can improve the performance of the compensator in over shoot case. In addition, the estimation of the valve residual life based on the level of stiction and effort required by the controller should be considered.

The presented approach represents an original contribution to the literature. It performs stiction compensation without a need for a prior knowledge on the process or the valve models and guarantees a smooth control of the stem movement with a low control effort. The proposed approach differs from previous adaptive methods as it uses stable FIR models and DE to find the appropriate parameters of the inverse model and handle nonlinear behavior of stiction.

Wireless sensor networks (WSNs) are periodically collecting data through randomly dispersed sensors (motes), which typically consume high energy in radio communication that mainly leans on data transmission within the network. Furthermore, dissemination mode in WSN usually produces noisy values, incorrect measurements or missing information that affect the behaviour of WSN. In this article, a Distributed Data Predictive Model (DDPM) was proposed to extend the network lifetime by decreasing the consumption in the energy of sensor nodes. It was built upon a distributive clustering model for predicting dissemination-faults in WSN. The proposed model was developed using Recursive least squares (RLS) adaptive filter integrated with a Finite Impulse Response (FIR) filter, for removing unwanted reflections and noise accompanying of the transferred signals among the sensors, aiming to minimize the size of transferred data for providing energy efficient. The experimental results demonstrated that DDPM reduced the rate of data transmission to ∼20%. Also, it decreased the energy consumption to 95% throughout the dataset sample and upgraded the performance of the sensory network by about 19.5%. Thus, it prolonged the lifetime of the network.

With the growing system‐on‐a‐chip (SOC) design complexity, SOC verification has become a major congestion. In this context, efficient and reliable verification environment is requested for SOC design before it is committed to production. The purpose of this paper is to judge whether the hardware and or software (HW/SW) co‐verification environment can handle SOC verification and provide the necessary performance in terms of co‐verification speed and throughput, power and resource consumption, timing analysis, etc.

A finite‐impulse‐response filter is utilized as a device‐under‐test to compare pure SW simulation, Modelsim simulator in this case, and HW/SW co‐verification approaches to decide on whether the HW/SW co‐verification environment can do work or not. In addition, the performance of the HW/SW co‐verification environment is estimated based on specifications such as co‐verification speed and throughput, power and resource consumption, and timing analysis.

From experiment results, conclusions can be drawn that the more complicated SOC is, the greater the potential speedup of the co‐verification approach over SW simulation is. However, the communication between SW and HW in HW/SW co‐verification system is a major congestion, which may offset the acceleration achieved by moving large computation from the SW to the HW side.

Performance estimation for the HW/SW co‐verification environment has been conducted in terms of co‐verification speed and throughput, power and resource consumption, timing analysis, etc.

The purpose of this paper is to find the best way to obtain the Sagnac phase shift in the output signal of open loop interferometric fiber optic gyroscopes (IFOGs). Also, the utilized digital filtering based on FIR kaiser window for implementing the digital signal processing part is evaluated.

The approach is based on implementing four kaiser FIR filters, the coefficients of which have been obtained from SPtool. They were simulated with SPtool in the Matlab 7.1.

The results show that the chosen computational method has reliable accuracy. On the other hand, it could require low‐computational effort, and it is a simple way which is important for the signal processors.

The limitation in this paper is that the designed filters have high order and they require much time; therefore, a high‐speed device is needed. For solving this problem, it is proposed to perform some estimation by experiments.

IFOGs are used in aircraft, missiles, and new civil fields such as automobile navigation, antenna stabilization, crane control, unmanned vehicle control, wind, and renewable energy platform stabilization.

There is no other paper which has explained mathematics of IFOG implementation in the signal processing part as completely as is done here.