Techniques of impedance matching for minimal PCB channel loss at 40 GBPS signal transmission

Chang Fei Yee (University Malaysia Perlis, Arau, Malaysia)
Muammar Mohamad Isa (University Malaysia Perlis, Arau, Malaysia)
Azremi Abdullah Al-Hadi (University Malaysia Perlis, Arau, Malaysia)
Mohd Khairuddin Md Arshad (University Malaysia Perlis, Arau, Malaysia)

Circuit World

ISSN: 0305-6120

Publication date: 5 August 2019

Abstract

Purpose

This paper aims to analyze the negative impact of surface mount (SMT) pad and imperfect via structure such as stub, pad, non-functional pad (NFP) and anti-pad on the signal integrity at 40 Gbps transmission on printed circuit board (PCB) due to impedance mismatch or discontinuity. The optimized modeling of via and SMT structures is performed to achieve minimal impedance mismatch and insertion loss less than 10 dB for six-inch full path transmission line between transmitter and receiver on PCB at Nyquist frequency 20 GHz.

Design/methodology/approach

This work is split into two phases. The first phase involves optimization of via and SMT structures in three-dimensional electromagnetic (3DEM) simulation using Hyperlynx Via Wizard and Keysight EMPro software, respectively, followed by analysis of time domain reflectometry (TDR) and insertion loss (Sdd21). Whereas, in the second phase, full path hybrid mode simulation involving vias for signal layer transition, a 6-inch PCB channel and SMT pads is performed using Keysight ADS software to observe the TDR, Sdd21 and eye diagram at 40 Gbps transmission.

Findings

Imperfect via and SMT structures have a negative effect on signal reflection and attenuation. The optimized via and SMT minimizes the impedance mismatch by 81 per cent and insertion loss by 4.5 dB, ultimately enlarging the eye diagram opening to achieve minimal data loss at receiver with 40 Gbps transmission.

Originality/value

The results of original empirical research work on signal integrity analysis that optimizes the PCB channel design to achieve 40 Gbps signal transmission are presented in this study. It serves as a reference guide for high-speed PCB layout design.

Keywords

Citation

Yee, C., Mohamad Isa, M., Abdullah Al-Hadi, A. and Md Arshad, M. (2019), "Techniques of impedance matching for minimal PCB channel loss at 40 GBPS signal transmission", Circuit World, Vol. 45 No. 3, pp. 132-140. https://doi.org/10.1108/CW-01-2019-0004

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Publisher

:

Emerald Publishing Limited

Copyright © 2019, Emerald Publishing Limited

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