A topology optimization of on-chip planar inductor based on evolutional on/off method and CMA-ES

Abstract

Purpose

There are few reports that evolutional topology optimization methods are applied to the conductor geometry design problems. This paper aims to propose an evolutional topology optimization method is applied to the conductor design problems of an on-chip inductor model.

Design/methodology/approach

This paper presents a topology optimization method for conductor shape designs. This method is based on the normalized Gaussian network-based evolutional on/off topology optimization method and the covariance matrix adaptation evolution strategy. As a target device, an on-chip planer inductor is used, and single- and multi-objective optimization problems are defined. These optimization problems are solved by the proposed method.

Findings

Through the single- and multi-objective optimizations of the on-chip inductor, it is shown that the conductor shapes of the inductor can be optimized based on the proposed methods.

Originality/value

The proposed topology optimization method is applicable to the conductor design problems in that the connectivity of the shapes is strongly required.

Citation

Sato, T. and Watanabe, K. (2024), "A topology optimization of on-chip planar inductor based on evolutional on/off method and CMA-ES", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 43 No. 4, pp. 920-931. https://doi.org/10.1108/COMPEL-10-2023-0503