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A variety of thick film planar inductors, designed for applications in the HF range, were printed from conductive PdAg and NiFe₂O₄ ferrite paste on alumina substrate. Pure ferrite powder with a nanometric particle size was used in the NiFe₂O₄ paste preparation. The ferrite thick film layer characterisation was performed on small spirals, after which the following inductor planar geometries were tested together with ferrite layers: meanders, spirals, bispirals and solenoid in plane. Their impedance was analysed with an impedance analyser in the MHz‐GHz range. The results obtained were compared with the properties of the smallest cubic inductors and with the literature data for planar inductors (theoretical and practical). A comparison was made of the L geometries printed. It was observed that better utilisation of the thick ferrite layers was achieved on L geometries with equally distributed windings over the thick ferrite layers.

Ni‐ferrite powder average grain size less than 0.9µm was used for the ferrite paste preparation. Ferrite paste was printed on Al2O3 substrate and fired 850°C/10min. After Ni‐ferrite thick film characterization had been done, simple planar inductor geometry, such as square spirals, were printed on it. Measurements were done, using an HP 4194A impedance analyser. The experimental results were summarized and compared with theoretical predictions given by the electromagnetic analysis using the method of current images for the reason of accounting the effect of magnetic substrate. The computer program, developed here, allows determination of the required thickness of the substrate which will produce inductance enhancement of the given permeability of the substrate material. The same results can also be used to determine the permeability of magnetic film or substrate quickly and are directly applicable to the design of the planar inductors.

This paper aims to introduce a technique for optimizing conductor dimensions for construction of helical planar inductor windings with reduced ac‐ and dc‐resistance. The loss reduction is evaluated on simulation and experimental level.

Helical planar windings are currently manufactured by forming each conductive and insulating layer individually. The conductive layers are only interconnected later to form the winding. This process allows greater freedom in selecting the optimum conductor dimensions on a per‐layer basis. Methods are proposed for sinusoidal and non‐sinusoidal current excitation waveforms and shaped windings are introduced for further loss reduction where conductors are in close proximity to air gaps in magnetic cores.

Traditional optimization of the conductor thickness used for foil wound inductors renders one single value used for each of the respective layers in the winding. This is a result of the manufacturing process involved in making traditional “barrel” windings. This optimization technique has simply been applied in planar inductors for the lack of alternatives up to now. It will be shown that large loss reduction may be achieved by manipulating the conductor dimensions of each layer individually.

A new approach to optimization problems verified experimentally offers more efficient inductors.

Multilayer aircore inductors fabricated in a range of interconnection technologies which are MCM compatible are presented and compared. These consist of thick‐film, low temperature cofired ceramic (LTCC), printed circuit board (PCB) and fine‐line plated copper on ceramic (copper plating). From a comparison of simulated and measured results, it can be concluded that a predictive design capability has been achieved for inductance and self‐resonant frequency (SRF). Modelling of AC resistance and Q requires further investigation.

Temperature humidity acceleration factors for surface conductance are obtained to relate the reliability of film conductors formed by different processes. Analytical expressions for acceleration factor are evolved for both screen‐printed and laser micromachined conductor samples. The rapid solidification of metal conductors due to laser micromachining and its effect on surface conductance are also studied. An analytical expression for the most common accelerated test condition (85°C, 85% relative humidity) is also derived for both screen‐printed and laser micromachined samples.

There are few reports that evolutional topology optimization methods are applied to the conductor geometry design problems. This paper aims to propose an evolutional topology optimization method is applied to the conductor design problems of an on-chip inductor model.

This paper presents a topology optimization method for conductor shape designs. This method is based on the normalized Gaussian network-based evolutional on/off topology optimization method and the covariance matrix adaptation evolution strategy. As a target device, an on-chip planer inductor is used, and single- and multi-objective optimization problems are defined. These optimization problems are solved by the proposed method.

Through the single- and multi-objective optimizations of the on-chip inductor, it is shown that the conductor shapes of the inductor can be optimized based on the proposed methods.

The proposed topology optimization method is applicable to the conductor design problems in that the connectivity of the shapes is strongly required.

A laser ablation technique has been used to fabricate conductor patterns on a 96% alumina substrate to evolve passive fine‐line components and structures. This paper reports the method of fabricating better fine‐line passive components for hybrid microelectronics application. The effect of a laser beam on the conductor and 96% alumina (Al₂O₃) substrate was studied in detail. Three predominant structures — namely debris, ablation border and irradiated bottom layer — were seen on the patterns. A detailed study of the dendritic growth caused by electrochemical migration on conductor lines fabricated by conventional screen printing and by laser ablation techniques is also reported.

To investigate the fabrication of integrated inductors on a liquid crystal polymer (LCP) substrate. To analyze the RF performance of the integrated inductors.

Fabrication of integrated inductors on a LCP substrate using an MCM‐D/L technique. A lumped element model of the integrated inductors is proposed. An analytical approach is used to extract the parameters in the model.

Integrated inductors on a LCP substrate have been fabricated using an MCM‐D/L technique. The conductor loss of the thin microstrip lines is the major factor degrading the Q‐value of the integrated inductors. A lumped element model of the integrated inductor is proposed. The parameters of the lumped element model can be extracted from the geometry of the integrated inductor. Further work will focus on increasing the conductor thickness from 500 nm to 5 μm.

The value of the paper lies in its description of the integration of inductors on a LCP substrate. It also describes how to extract parameters of the lumped element model of the integrated inductors from the geometry.

Present 3D electromagnetic simulators have high accuracy but they are time and memory expensive. Owing to a fast and simple expression for inductance is also necessary for initial inductor design. In this paper, new efficient methods for total inductance calculation of meander inductor, are given. By using an algorithm, it is possible to predict correctly all inductance variations introduced by varying geometry parameters such as number of turns, width of conductor or spacing between conductors.

The starting point for the derivation of the recurrent formula is Greenhouse theory. Greenhouse decomposed inductor into its constituent segments. Meander inductor is divided into straight conductive segments. Then the total inductance of the meander inductor is a sum of self‐inductances of all segments and the negative and positive mutual inductances between all combinations of straight segments. The monomial equation for the total inductance of meander inductor has been obtained by fitting procedure. The fitting technique, using the method of least squares, finds the parameters of the monomial equation that minimize the sum of squares of the error between the accurate data and fitted equation. The paper presents new expression for inductance of meander inductor, in the monomial form, which is suitable for optimization via geometric programming. The computed inductances are compared with measured data from the literature.

The first, recurrent, expression has the advantage that it indicates to the designer how the relative contributions of self, positive, and negative mutual inductance are related to the geometrical parameters. The second expression presents the inductance of the meander inductor in the monomial form, so that the optimization of the inductor can be done by procedure of the geometric programming. Simplicity and relatively good accuracy are the advantages of this expression, but on the other hand the physical sense of the expression is being lost. Thus, the effects of various geometry parameters on inductance are analyzed using two expressions and the software tool INDCAL.

Applied flexible efficient methods for inductance calculation of meander inductor are able to significantly increase the speed of RF and sensor integrated circuit design.

For the first time a simple expression for fast inductance calculation for meander inductor in monomial form is presented. It is explained how such an expression is generated, which can be directly implemented in circuit simulators.

The purpose of this study is to develop a high-quality factor fractal inductor for wireless applications such as satellite, WLAN, Bluetooth, microwave, radar and cellular phone.

The Hilbert fractal curve is used in the implementation of the proposed inductor. In the proposed inductor, the metal width has split into multiple paths based on the skin depth of the metal. The simulations of the proposed inductor are performed in 180 nm CMOS technology using the Advanced Design System EM simulator.

The multipath technique reduces the skin effects and proximity effects, which, in turn, decreases the series resistance of the inductor and attains high-quality factor over conventional fractal inductor for the equal on-chip area.

The width of the path has chosen higher than the skin depth of the metal for a required operating frequency. Due to cost constraints, the manufacturing of the proposed fractal inductor is limited to a single layer.

The proposed inductor will be useful for the implementation of critical building blocks of radio frequency integrated circuits and monolithic microwave integrated circuits such as low-noise amplifiers, voltage-controlled oscillators, mixers, filters and power amplifiers.

This paper presents for the first time the use of a multipath technique for the fractal inductors to enhance the quality factor.