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PAD design reliability for SMD passives

Milos Dusek (National Physical Laboratory, Teddington, UK)
Ivan Szendiuch (Technical University of Brno, Department of Microelectronics, Brno, Czech Republic)
Petr Szuscik (Entrelec Vemer, Brno, Czech Republic)

Microelectronics International

ISSN: 1356-5362

Article publication date: 1 April 2000



Investigates the influence of land pattern pad designs and solder volume on reliability of solder joint attachments for surface mounted passive chip devices. All boards were thermal cycled and periodically tested to induce a damage mechanism in less time than in real service use. The difference in the number of failures for different pad designs and for different stencil thicknesses was recorded. Failure analysis with respect to stencil thickness and position of resistor on board is studied and a new approach for the comparison of resistor reliability by using Weibull distribution is shown. The time period for this testing was kept to a minimum by accelerated ageing of tested samples. This test aims to predict the onset of the wear‐out period under the normal conditions of service. The results from measurements during thermal cycling are also given and the basic rules for practical application are summarised.



Dusek, M., Szendiuch, I. and Szuscik, P. (2000), "PAD design reliability for SMD passives", Microelectronics International, Vol. 17 No. 1, pp. 8-12.




Copyright © 2000, MCB UP Limited

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