Cadence Encounter Technologies enable Open-Silicon to reach 2.2 GHz performance on 28 nm ARM dual-core Cortex-A9 processor

Citation

(2013), "Cadence Encounter Technologies enable Open-Silicon to reach 2.2 GHz performance on 28 nm ARM dual-core Cortex-A9 processor", Microelectronics International, Vol. 30 No. 2. https://doi.org/10.1108/mi.2013.21830baa.003

Cadence Encounter Technologies enable Open-Silicon to reach 2.2 GHz performance on 28 nm ARM dual-core Cortex-A9 processor

Article Type: Industry news From: Microelectronics International, Volume 30, Issue 2

Cadence Design Systems, Inc. have announced that Open-Silicon, Inc., a leading semiconductor design and manufacturing company, has leveraged the latest innovations from the Cadence^® Encounter^® RTL-to-signoff flow to achieve 2.2 GHz performance on a 28-nm hardening of an ARM^® dual-core Cortex™-A9 processor.

Open-Silicon used the latest “Encounter digital” RTL-to-signoff products for the processor core which is targeted for mobile computing applications, including RTL Compiler-Physical (RC-Physical) and Encounter Digital Implementation (EDI) System. EDI System features advanced GigaOpt optimization and Clock Current Optimization (CCOpt) technologies, which, together with RC-Physical, helped reduce the design area by 10 percent, clock tree power by 33 percent and overall leakage power by 27 percent compared to a prior flow, while accelerating design closure by two weeks.

Open-Silicon’s chips go into leading-edge products where power, performance, and area (PPA), and time-to-parts are paramount. Open-Silicon’s extensive experience with processor implementations across many verticals, including networking/telecom, storage and computing, enables turnkey ARM technology-based SoC design. By leveraging the Center of Excellence (CoE) for ARM technology-based designs at Open-Silicon and Cadence optimized RTL-to-signoff flows, customers are now able to achieve market-differentiating performance and power efficiencies in their ARM technology-based products.

The Cadence Encounter RTL-to-signoff flow has been significantly optimized for ARM processor-based design, helping design teams optimize PPA for the world’s most advanced high-performance, and power efficient designs. The flow includes Encounter RC-Physical, EDI System, and signoff-proven Cadence QRC Extraction, and ETS. The new GigaOpt technology inside EDI System produces high-quality results faster than traditional optimization engines by harnessing the power of multiple CPUs. In addition, the integrated CCOpt technology unifies clock tree synthesis with logic/physical optimization resulting in significant PPA improvements.

As a result of this success, Open-Silicon has standardized on the Encounter RTL-to-signoff flow in its CoE for hardening high-performance ARM technology-based SoCs.