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TSMC selects Synopsys HSIM Simulator for sub-40 nm memory IP characterisation
Article Type: Industry news From: Microelectronics International, Volume 27, Issue 1
Synopsys, Inc. have announced that TSMC has adopted Synopsys' HSIM® hierarchical FastSPICE circuit simulator for its sub-40 nm memory intellectual property (IP) characterisation flow. The HSIM simulator will be deployed for TSMC advanced SRAM compilers for timing, power simulation, dynamic IR drop and EM analysis, as well as for full-chip simulation with extracted package models. Using the latest version of the HSIM tool, TSMC is able to improve memory characterisation throughput by ten times while achieving tight correlation to silicon measurements.
“At 40 nm nodes and beyond, post-layout parasitic data, power reliability and leakage need to be accounted for when characterising memories,” said ST Juang, Senior Director of Design Infrastructure Marketing at TSMC. “We had adopted HSIM for our memory IP characterisation at previous technology nodes, and after extensive evaluation we chose HSIM for our sub-40 nm flow based on its advanced technologies for post-layout analysis and its ability to deliver accurate simulation results while maintaining fast throughput for our largest memory compilers.”
As layout geometries shrink, accurate characterisation of memories becomes more of a challenge. Previous methodologies that have employed critical path and cut netlists are no longer adequate to accurately verify the impact of cross-coupling effects and layout parasitics. As a result, more customers have adopted the method of verifying the entire memory design, including the chip packaging, for sub-40 nm process nodes. HSIM, the technology-leading FastSPICE circuit simulator, addresses this challenge by delivering accurate simulation results with superior performance. HSIM provides a comprehensive solution for circuit simulation, post-layout analysis, reliability analysis and electrical rule checking.