The effects of polysilicon emitter on the high frequency performance of bipolar transistors have been investigated numerically. The presence of polysilicon grain boundaries was found to slow down the response of the device. This resulted in a lower fT for polysilicon emitter bipolar transistors with a clean polysilicon/ mono‐crystalline silicon interface compared to conventional transistors with an identical emitter‐base junction depth. The interfacial oxide layer that could exist at the polysilicon/mono‐crystalline silicon interface can, depending on the relative thickness of the polysilicon and mono‐crystalline silicon emitter regions, either improve or deteriorate the high frequency performance of the device. For a mono‐crystalline silicon emitter region that is much thinner than the polysilicon emitter region, the lower the tunnelling probability of the interfacial oxide layer the better is the improvement in fT. However, if the thickness of the mono‐crystalline silicon emitter region is made larger with respect to the polysilicon emitter region, the converse can be true.
CHOR, E.F. and TAN, L.S. (1991), "A NUMERICAL STUDY OF THE DEPENDENCE OF UNITY GAIN BANDWIDTH fT ON POLYSILICON EMITTER IN BIPOLAR TRANSISTORS", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 10 No. 4, pp. 553-562. https://doi.org/10.1108/eb051730
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