Fundamental engineering limits to very high speed electronics switching systems are employed. These limitations are caused by packaging and interconnection constraints, as well as device switching speed. From the device viewpoint, reactive parasitics caused by the packaging/interconnection scenario are discussed. From the systems level perspective, overall delay, delay variance and power consumption are explored. The important problem of clock distribution in high speed synchronous digital systems is discussed. These limitations are then revisited with photonics implementation in mind. Comparisons are made between the electrical and photonic approaches. Some engineering limits to the photonic alternative are laid out.
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